Reconfigurable Multifunctional van der Waals Ferroelectric Devices and Logic Circuits

In this work, we demonstrate the suitability of Reconfigurable Ferroelectric Field-Effect- Transistors (Re-FeFET) for designing non-volatile reconfigurable logic-in-memory circuits with multifunctional capabilities. Modulation of the energy landscape within a homojunction of a 2D tungsten diselenide (WSe$_2$) layer is achieved by independently controlling two split-gate electrodes made of a ferroelectric 2D copper indium thiophosphate (CuInP$_2$S$_6$) layer. Controlling the state encoded in the Program Gate enables switching between p, n and ambipolar FeFET operating modes. The transistors exhibit on-off ratios exceeding 10$^6$ and hysteresis windows of up to 10 V width. The homojunction can change from ohmic-like to diode behavior, with a large rectification ratio of 10$^4$. When programmed in the diode mode, the large built-in p-n junction electric field enables efficient separation of photogenerated carriers, making the device attractive for energy harvesting applications. The implementation of the Re-FeFET for reconfigurable logic functions shows how a circuit can be reconfigured to emulate either polymorphic ferroelectric NAND/AND logic-in-memory or electronic XNOR logic with long retention time exceeding 10$^4$ seconds. We also illustrate how a circuit design made of just two Re-FeFETs exhibits high logic expressivity with reconfigurability at runtime to implement several key non-volatile 2-input logic functions. Moreover, the Re-FeFET circuit demonstrates remarkable compactness, with an up to 80% reduction in transistor count compared to standard CMOS design. The 2D van de Waals Re-FeFET devices therefore exhibit groundbreaking potential for both More-than-Moore and beyond-Moore future of electronics, in particular for an energy-efficient implementation of in-memory computing and machine learning hardware, due to their multifunctionality and design compactness.Comment: 23 pages, 5 figures; Supporting Information: 12 pages, 6 figure

Characterization of Electrophoretic Deposited Zinc Oxide Nanopartices for the Fabrication of Next-Generation Nanoscale Electronic Applications

Several reports state that it is crucial to analyze nanoscale semiconductor materials and devices with potential benefits to meet the need for next-generation nanoelectronics, bio, and nanosensors. The progress in the electronics field is as significant now, with modern technology constantly evolving and a greater focus on more efficient robust optoelectronic applications. This dissertation focuses on the study and examination of the practicality of Electrophoretic Deposition (EPD) of zinc oxide (ZnO) nanoparticles (NPs) for use in semiconductor applications. The feasibility of several synthesized electrolytes, with and without surfactants and APTES surface functionalization, is discussed. The primary objective of this study is to demonstrate that the electrophoretic method for depositing ZnO NPs can also be used to produce ZnO films onto p-type silicon, functionalized p-type silicon, and aluminum substrates. This investigation uses ZnO NPs deposited at room temperature onto silicon, functionalized silicon, and aluminum substrates via EPD. The experimental work examines EPD solution formulations, EPD optimization for ZnO NP coverage, imaging of the surfaces, and electrical characterizations. Thin films produced were examined using Scanning Electron Microscopy (SEM), Raman Spectroscopy (RS), Ultraviolent Photoelectron Spectroscopy (UPS), and Atomic Force Microscopy (AFM), electrical impedance, and current-voltage (I-V) measurements. The results obtained are viewed in the context of providing valuable information in the ongoing search for reproducible and robust yet economical means of NP and thin-film deposition. This work fabricates a proof-of-concept pn junction composed of n-type ZnO NPs electrophoretically deposited onto p-type Si. This investigation presents a potential opportunity for integrating this deposition method into applications where ZnO contributes to the reliability, affordability, and highly increased sensitivity needed for the next generation of nanoscale devices and systems. The EPD of ZnO nanoscale thin films is important to several research areas, including biosensors, photophilic dye-sensitized solar cells, optoelectronic devices, and thin-film transistors. ZnO NPs have recently attracted attention due to their excellent optoelectronic performance and low cost of production [1-11]. Combining EPD with ZnO NPs will result in a more accessible technique of nanomaterial deposition, research tools for thin films and nanostructures, and improved materials for next-generation electronic

Miniaturized Silicon Photodetectors

Silicon (Si) technologies provide an excellent platform for the design of microsystems where photonic and microelectronic functionalities are monolithically integrated on the same substrate. In recent years, a variety of passive and active Si photonic devices have been developed, and among them, photodetectors have attracted particular interest from the scientific community. Si photodiodes are typically designed to operate at visible wavelengths, but, unfortunately, their employment in the infrared (IR) range is limited due to the neglectable Si absorption over 1100 nm, even though the use of germanium (Ge) grown on Si has historically allowed operations to be extended up to 1550 nm. In recent years, significant progress has been achieved both by improving the performance of Si-based photodetectors in the visible range and by extending their operation to infrared wavelengths. Near-infrared (NIR) SiGe photodetectors have been demonstrated to have a “zero change” CMOS process flow, while the investigation of new effects and structures has shown that an all-Si approach could be a viable option to construct devices comparable with Ge technology. In addition, the capability to integrate new emerging 2D and 3D materials with Si, together with the capability of manufacturing devices at the nanometric scale, has led to the development of new device families with unexpected performance. Accordingly, this Special Issue of Micromachines seeks to showcase research papers, short communications, and review articles that show the most recent advances in the field of silicon photodetectors and their respective applications

Design Automation and Application for Emerging Reconfigurable Nanotechnologies

In the last few decades, two major phenomena have revolutionized the electronic industry – the ever-increasing dependence on electronic circuits and the Complementary Metal Oxide Semiconductor (CMOS) downscaling. These two phenomena have been complementing each other in a way that while electronics, in general, have demanded more computations per functional unit, CMOS downscaling has aptly supported such needs. However, while the computational demand is still rising exponentially, CMOS downscaling is reaching its physical limits. Hence, the need to explore viable emerging nanotechnologies is more imperative than ever. This thesis focuses on streamlining the existing design automation techniques for a class of emerging reconfigurable nanotechnologies. Transistors based on this technology exhibit duality in conduction, i.e. they can be configured dynamically either as a p-type or an n-type device on the application of an external bias. Owing to this dynamic reconfiguration, these transistors are also referred to as Reconfigurable Field-Effect Transistors (RFETs). Exploring and developing new technologies just like CMOS, require tackling two main challenges – first, design automation flow has to be modified to enable tailor- made circuit designs. Second, possible application opportunities should be explored where such technologies can outsmart the existing CMOS technologies. This thesis targets the above two objectives for emerging reconfigurable nanotechnologies by proposing approaches for enabling an Electronic Design Automation (EDA) flow for circuits based on RFETs and exploring hardware security as an application that exploits the transistor-level dynamic reconfiguration offered by this technology. This thesis explains the bottom-up approach adopted to propose a logic synthesis flow by identifying new logic gates and circuit design paradigms that can particularly exploit the dynamic reconfiguration offered by these novel nanotechnologies. This led to the subsequent need of finding natural Boolean logic abstraction for emerging reconfigurable nanotechnologies as it is shown that the existing abstraction of negative unate logic for CMOS technologies is sub-optimal for RFETs-based circuits. In this direction, it has been shown that duality in Boolean logic is a natural abstraction for this technology and can truly represent the duality in conduction offered by individual transistors. Finding this abstraction paved the way for defining suitable primitives and proposing various algorithms for logic synthesis and technology mapping. The following step is to explore compatible physical synthesis flow for emerging reconfigurable nanotechnologies. Using silicon nanowire-based RFETs, .lef and .lib files have been provided which can provide an end-to-end flow to generate .GDSII file for circuits exclusively based on RFETs. Additionally, new approaches have been explored to improve placement and routing for circuits based on reconfigurable nanotechnologies. It has been demonstrated how these approaches led to superior results as compared to the native flow meant for CMOS. Lastly, the unique property of transistor-level reconfiguration offered by RFETs is utilized to implement efficient Intellectual Property (IP) protection schemes against adversarial attacks. The ability to control the conduction of individual transistors can be argued as one of the impactful features of this technology and suitably fits into the paradigm of security measures. Prior security schemes based on CMOS technology often come with large overheads in terms of area, power, and delay. In contrast, RFETs-based hardware security measures such as logic locking, split manufacturing, etc. proposed in this thesis, demonstrate affordable security solutions with low overheads. Overall, this thesis lays a strong foundation for the two main objectives – design automation, and hardware security as an application, to push emerging reconfigurable nanotechnologies for commercial integration. Additionally, contributions done in this thesis are made available under open-source licenses so as to foster new research directions and collaborations.:Abstract List of Figures List of Tables 1 Introduction 1.1 What are emerging reconfigurable nanotechnologies? 1.2 Why does this technology look so promising? 1.3 Electronics Design Automation 1.4 The game of see-saw: key challenges vs benefits for emerging reconfigurable nanotechnologies 1.4.1 Abstracting ambipolarity in logic gate designs 1.4.2 Enabling electronic design automation for RFETs 1.4.3 Enhanced functionality: a suitable fit for hardware security applications 1.5 Research questions 1.6 Entire RFET-centric EDA Flow 1.7 Key Contributions and Thesis Organization 2 Preliminaries 2.1 Reconfigurable Nanotechnology 2.1.1 1D devices 2.1.2 2D devices 2.1.3 Factors favoring circuit-flexibility 2.2 Feasibility aspects of RFET technology 2.3 Logic Synthesis Preliminaries 2.3.1 Circuit Model 2.3.2 Boolean Algebra 2.3.3 Monotone Function and the property of Unateness 2.3.4 Logic Representations 3 Exploring Circuit Design Topologies for RFETs 3.1 Contributions 3.2 Organization 3.3 Related Works 3.4 Exploring design topologies for combinational circuits: functionality-enhanced logic gates 3.4.1 List of Combinational Functionality-Enhanced Logic Gates based on RFETs 3.4.2 Estimation of gate delay using the logical effort theory 3.5 Invariable design of Inverters 3.6 Sequential Circuits 3.6.1 Dual edge-triggered TSPC-based D-flip flop 3.6.2 Exploiting RFET’s ambipolarity for metastability 3.7 Evaluations 3.7.1 Evaluation of combinational logic gates 3.7.2 Novel design of 1-bit ALU 3.7.3 Comparison of the sequential circuit with an equivalent CMOS-based design 3.8 Concluding remarks 4 Standard Cells and Technology Mapping 4.1 Contributions 4.2 Organization 4.3 Related Work 4.4 Standard cells based on RFETs 4.4.1 Interchangeable Pull-Up and Pull-Down Networks 4.4.2 Reconfigurable Truth-Table 4.5 Distilling standard cells 4.6 HOF-based Technology Mapping Flow for RFETs-based circuits 4.6.1 Area adjustments through inverter sharings 4.6.2 Technology Mapping Flow 4.6.3 Realizing Parameters For The Generic Library 4.6.4 Defining RFETs-based Genlib for HOF-based mapping 4.7 Experiments 4.7.1 Experiment 1: Distilling standard-cells from a benchmark suite 4.7.2 Experiment 2A: HOF-based mapping . 4.7.3 Experiment 2B: Using the distilled standard-cells during mapping 4.8 Concluding Remarks 5 Logic Synthesis with XOR-Majority Graphs 5.1 Contributions 5.2 Organization 5.3 Motivation 5.4 Background and Preliminaries 5.4.1 Terminologies 5.4.2 Self-duality in NPN classes 5.4.3 Majority logic synthesis 5.4.4 Earlier work on XMG 5.4.5 Classification of Boolean functions 5.5 Preserving Self-Duality 5.5.1 During logic synthesis 5.5.2 During versatile technology mapping 5.6 Advanced Logic synthesis techniques 5.6.1 XMG resubstitution 5.6.2 Exact XMG rewriting 5.7 Logic representation-agnostic Mapping 5.7.1 Versatile Mapper 5.7.2 Support of supergates 5.8 Creating Self-dual Benchmarks 5.9 Experiments 5.9.1 XMG-based Flow 5.9.2 Experimental Setup 5.9.3 Synthetic self-dual benchmarks 5.9.4 Cryptographic benchmark suite 5.10 Concluding remarks and future research directions 6 Physical synthesis flow and liberty generation 6.1 Contributions 6.2 Organization 6.3 Background and Related Work 6.3.1 Related Works 6.3.2 Motivation 6.4 Silicon Nanowire Reconfigurable Transistors 6.5 Layouts for Logic Gates 6.5.1 Layouts for Static Functional Logic Gates 6.5.2 Layout for Reconfigurable Logic Gate 6.6 Table Model for Silicon Nanowire RFETs 6.7 Exploring Approaches for Physical Synthesis 6.7.1 Using the Standard Place & Route Flow 6.7.2 Open-source Flow 6.7.3 Concept of Driver Cells 6.7.4 Native Approach 6.7.5 Island-based Approach 6.7.6 Utilization Factor 6.7.7 Placement of the Island on the Chip 6.8 Experiments 6.8.1 Preliminary comparison with CMOS technology 6.8.2 Evaluating different physical synthesis approaches 6.9 Results and discussions 6.9.1 Parameters Which Affect The Area 6.9.2 Use of Germanium Nanowires Channels 6.10 Concluding Remarks 7 Polymporphic Primitives for Hardware Security 7.1 Contributions 7.2 Organization 7.3 The Shift To Explore Emerging Technologies For Security 7.4 Background 7.4.1 IP protection schemes 7.4.2 Preliminaries 7.5 Security Promises 7.5.1 RFETs for logic locking (transistor-level locking) 7.5.2 RFETs for split manufacturing 7.6 Security Vulnerabilities 7.6.1 Realization of short-circuit and open-circuit scenarios in an RFET-based inverter 7.6.2 Circuit evaluation on sub-circuits 7.6.3 Reliability concerns: A consequence of short-circuit scenario 7.6.4 Implication of the proposed security vulnerability 7.7 Analytical Evaluation 7.7.1 Investigating the security promises 7.7.2 Investigating the security vulnerabilities 7.8 Concluding remarks and future research directions 8 Conclusion 8.1 Concluding Remarks 8.2 Directions for Future Work Appendices A Distilling standard-cells B RFETs-based Genlib C Layout Extraction File (.lef) for Silicon Nanowire-based RFET D Liberty (.lib) file for Silicon Nanowire-based RFET

Two-Dimensional Electronics and Optoelectronics

The discovery of monolayer graphene led to a Nobel Prize in Physics being awarded in 2010. This has stimulated further research on a wide variety of two-dimensional (2D) layered materials. The coupling of metallic graphene, semiconducting 2D transition metal dichalcogenides (TMDCs) and black phosphorus have attracted a tremendous amount of interest in new electronic and optoelectronic applications. Together with other 2D materials, such as the wide band gap boron nitride nanosheets (BNNSs), all these 2D materials have led towards an emerging field of van der Waal 2D heterostructures. The papers in this book were originally published by Electronics (MDPI) in a Special Issue on “Two-Dimensional Electronics and Optoelectronics”. The book consists of eight papers, including two review articles, covering various pertinent and fascinating issues concerning 2D materials and devices. Further, the potential and the challenges of 2D materials are discussed, which provide up to date guidance for future research and development

Van der Waals Heterostructures based on Two-dimensional Ferroelectric and Ferromagnetic Layers

Two-dimensional (2D) van der Waals (vdW) crystals provide a platform for studies of novel phenomena and promising applications beyond traditional systems. This PhD thesis focuses on vertical 2D vdW heterostructures, including ferroelectric semiconductor junctions (FSJs), p-n junction diodes, and magnetic tunnel junctions (MTJs). These have potential for non-volatile memories, ultraviolet (UV) photosensing and low-power electronics. The ferroelectric polarization of the vdW semiconductor α-In2Se3 in graphene/α-In2Se3/graphene FSJs was switched by the bias voltage, thus producing memristive effects in the transport characteristics. These can be modified by light due to screening of the polarization by photocreated carriers. The FSJs demonstrated a high photoresponsivity (up to ~ 10^6 A/W) and a relatively fast modulation (down to ~ 0.2 ms) of the photocurrent. The graphene/p-GaSe/n-In2Se3/graphene heterostructures were used to investigate novel mechanisms for the detection of UV light. The p-GaSe/n-In2Se3 type-II band alignment and the electric field at the vdW interfaces were found to be beneficial to suppress carrier recombination and enhance the UV-photoresponse. Finally, the Fe3GaTe2/WSe2/Fe3GaTe2 MTJs exhibited an ideal tunnelling behaviour with a tunnel magnetoresistance (TMR) signal as large as 85 % at room temperature, breaking through the bottleneck of previous vdW MTJs that worked only at low temperatures (T < 300 K). The findings of this work offer opportunities for further developments, including the optimization of device structures and their studies towards enhanced functionalities beyond the current state of the art

Novel Materials and Devices for Terahertz Detection and Emission for Sensing, Imaging and Communication

Technical advancement is required to attain a high data transmission rate, which entails expanding beyond the currently available bandwidth and establishing a new standard for the highest data rates, which mandates a higher frequency range and larger bandwidth. The THz spectrum (0.1-10 THz) has been considered as an emerging next frontier for the future 5G and beyond technology. THz frequencies also offer unique characteristics, such as penetrating most dielectric materials like fabric, plastic, and leather, making them appealing for imaging and sensing applications. Therefore, employing a high-power room temperature, tunable THz emitters, and a high responsivity THz detector is essential. Dyakonov-theory Shur\u27s was applied in this dissertation to achieve tunable THz detection and emission by plasma waves in high carrier density channels of field-effect devices. The first major contribution of this dissertation is developing graphene-based THz plasmonics detector with high responsivity. An upside-down free-standing graphene in a field effect transistor based resonant room temperature THz detector device with significantly improved mobility and gate control has been presented. The highest achieved responsivity is ~3.1kV/W, which is more than 10 times higher than any THz detector reported till now. The active region is predominantly single-layer graphene with multi-grains, even though the fabricated graphene THz detector has the highest responsivity. The challenges encountered during the fabrication and measurement of the graphene-based detector have been described, along with a strategy to overcome them while preserving high graphene mobility. In our new design, a monolayer of hBN underneath the graphene layer has been deposited to increase the mobility and electron concentration rate further. We also investigated the diamond-based FETs for their potential characteristics as a THz emitters and detectors. Diamond\u27s wide bandgap, high breakdown field, and high thermal conductivity attributes make it a potential semiconductor material for high voltage, high power, and high-temperature operation. Diamond is a good choice for THz and sub-THz applications because of its high optical phonon scattering and high momentum relaxation time. Numerical and analytical studies of diamond materials, including p-diamond and n-diamond materials, are presented, indicating their effectiveness as a prospective contender for high temperature and high power-based terahertz applications These detectors are expected to be a strong competitor for future THz on-chip applications due to their high sensitivity, low noise, tunability, compact size, mobility, faster response time, room temperature operation, and lower cost. Furthermore, when plasma wave instabilities are induced with the proper biasing, the same devices can be employed as THz emitters, which are expected to have a higher emission power. Another key contribution is developing a method for detecting counterfeit, damaged, forged, or defective ICs has been devised utilizing a new non-destructive and unobtrusive terahertz testing approach to address the crucial point of hardware cybersecurity and system reliability. The response of MMICs, VLSI, and ULSIC to incident terahertz and sub-terahertz radiation at the circuit pins are measured and analyzed using deep learning. More sophisticated terahertz response profiles and signatures of specific ICs can be created by measuring a more significant number of pins under different frequencies, polarizations, and depth of focus. The proposed method has no effect on ICs operation and could provide precise ICs signatures. The classification process between the secure and unsecure ICs images has been explained using data augmentation and transfer learning-based convolution neural network with ~98% accuracy. A planar nanomatryoshka type core-shell resonator with hybrid toroidal moments is shown both experimentally and analytically, allowing unique characteristics to be explored. This resonator may be utilized for accurate sensing, immunobiosensing, quick switching, narrow-band filters, and other applications