Novel approaches in current-feedback operational amplifier design

The aim of this research programme was to design and develop a novel bipolar junction transistor Current Feedback Operational Amplifier (CFOA) with a good Common-Mode Rejection Ratio (CMRR), suitable for radio frequency (RF) applications. This research focused on investigation of the established CFOA with the emphases of improving CMRR, bandwidth, Voltage-Offset and Slew-rate performance. The majority of the results of this work have been reported by the author in references [11 to [6]. Initially a thorough analysis of the conventional CFOA was undertaken to provide an in depth understanding of the amplifier's operation, and this work revealed that the main shortcomings of the CFOA are in the design of the input stage. This initial study focussed on establishing reasons for the poor DC offset-voltage performance and CMRR and confirmed that these designs have inherently poor performance in these two elements. The analysis was carried out using both theoretical modelling and computer simulation. Using this analysis of the conventional CFOA as a benchmark, various novel circuit techniques were investigated. Several new input circuits for the CFOA were proposed with respect to improving the three previously mentioned key characteristics, viz., CMRR, offset voltage, and slew-rate. The first technique explored is based on floating the entire input stage of the CFOA which yielded significant improvements in CMRR, Offset-Voltage and bandwidth, and the results of this workwere published in [11, [2], and P). Based on these initial findings a second major development was undertaken. This time a bootstrapping technique was employed to key sections of the input stage, leading to new, simplified input circuit topology. This development leads to low DC offset voltage, wide bandwidth and high CNIRR, as well as improved gain accuracy, and was published by the author in [4,5]. A logical approach to the different input stage architectures examined by the author resulted in identification of a hierarchy of 6 different input CFOA circuit designs and a comparative study was undertaken showing their relative performance in respect of CMRR, Offset-Voltage and Slew-rate. This work was presented by the author, [6]

Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter

This work aims to model the effect of the input offset voltage of an operational amplifier on the performance of a high-precision, voltage-mode, resistor-based multiplying digital-to-analog converter (M-DAC). Based on the model, a high precision current buffer is proposed to isolate the resistor ladder from the operational amplifier. A 14-bit M-DAC operating with a ±1V reference of the proposed architecture. Post-layout simulations show that the proposed architecture reduces the offset voltage to an offset error in the DAC transfer function. The maximum DNL is maintained at -0.385 LSB for an input offset voltage of up to 60mV (1024 LSB). The current buffer also introduces an inversion of the output voltage, yielding a non-inverted output. This alleviates the need for an additional high precision op-amp to invert the output voltage

An electrocardiogram readout circuit based on CMOS operational floating current conveyor

Electrocardiogram (ECG) is used in diagnosing heart diseases. It is designed as integration between current-mode instrumentation amplifiers (CMIA) and low pass filter (LPF). Normal heart behavior can be identified simply by normal ECG that consists of signal while heart disorder can be recognized by having differences in the features of their corresponding ECG waveform. A novel integrated CMOS-based operational floating current conveyor (OFCC) circuit is proposed. OFCC is a five port general purpose analog building block which combines all the features of different current mode devices such as the second generation current conveyor (CCII), the current feedback operational amplifier (CFA), and the operational floating conveyor (OFC). The OFFC is modeled and simulated using UMC 130nm CMOS technology kit in Cadence with a supply voltage 1.2V. The ECG readout circuit has been designed using the proposed OFCC as a building block. The advantages of this: it is integrated, noise factor is small as the proposed OFCC has the lowest input noise voltage and the layout is simple as it is a single block that can be repeated several times

Design and Implementation of a Signal Conditioning Operational Amplifier for a Reflective Object Sensor

Industrial systems often require the acquisition of real-world analog signals for several applications. Various physical phenomena such as displacement, pressure, temperature, light intensity, etc. are measured by sensors, which is a type of transducer, and then converted into a corresponding electrical signal. The electrical signal obtained from the sensor, usually a few tens mV in magnitude, is subsequently conditioned by means of amplification, filtering, range matching, isolation etc., so that the signal can be rendered for further processing and data extraction. This thesis presents the design and implementation of a general purpose op amp used to condition a reflective object sensor’s output. The op amp is used in a non-inverting configuration, as a current-to-voltage converter to transform a phototransistor current into a usable voltage. The op amp has been implemented using CMOS architecture and fabricated in AMI 0.5-µm CMOS process available through MOSIS. The thesis begins with an overview of the various circuits involving op amps used in signal conditioning circuits. Owing to the vast number of applications for sensor signal conditioning circuits, a brief discussion of an industrial sensor circuit is also illustrated. This is followed by the complete design of the op amp and its implementation in the data acquisition circuit. The op amp is then characterized using simulation results. Finally, the test setup and the measurement results are presented. The thesis concludes with an overview of some possible future work on the sensor-op amp data acquisition circuit

Out-of-Loop Compensation Method for Op-Amps Driving Heavy Capacitive Loads

It is well known that real op-amps do not share most of the desirable characteristics of an ideal one, particularly those of gain and output impedance. When presented with a capacitive load, such as a MOSFET or ADC, feedback in an op-amp circuit can quickly become unstable. This thesis studies and characterizes an op-amp’s output impedance and how its interaction with this type of load creates a parasitic pole which leads to instability. Applying ideas from feedback control theory, a model for studying the problem is developed from which a generalized method for compensating the undesirable circumstance is formulated. Even in a zero-input state, many real op-amps driving capacitive loads can experience unforced oscillations. A case study is performed with three commonly used devices. First, the output impedance is determined by its dependence on the unity-gain bandwidth, load capacitance, and oscillation frequency. It is fitted into a second-order feedback control model that allows for an analytical study of the problem. It is then shown that a carefully designed passive network can be introduced between the load and op-amp to obtain a properly damped system free of oscillation and well-behaved. Using a shunt resistor is a known and commonly used method for lowering an op-amp’s output impedance to gain stability. This work considers the converse addition of a series capacitor to instead lower the load capacitance seen by the op-amp, a seemingly complementary method that achieves the same goal. A generalized, composite compensation method is developed that uses both the shunt resistor and series capacitor– a strategy not yet found in literature. Relevant formulas for damping ratio and natural frequency are derived that allow the design of a passive compensation network. Furthermore, tradeoffs between compensation, voltage swing, current consumption, and power usage are considered. An emphasis is placed on comparing simulated versus real circuits to highlight the fact that any problem is much worse in real-life than in a simulation. SPICE models and programs aim to de-idealize certain device characteristics, but often cannot account for environmental conditions and manufacturing variance. Thus, an importance is placed on experimental verification guided by simulations

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Developing a framework of non-fatal occupational injury surveillance for risk control in palm oil mills

Non-fatal occupational injury (NFOI) and its risk factors have become a current global concern. The need of research towards the relationship between occupational injury and its risk factor is essential, to fulfil the purpose and setting the priority of implementing safety preventive approaches at workplace. This research intended to develop a framework of NFOI surveillance by using epidemiological data, noise exposure data and NFOI data among palm oil mills’ workers. A total of 420 respondents who assigned in operation and processing areas (OP) (n=333) and general or office workers (n=87) had voluntary participated in this research. A questionnaire session with respondents was held to obtain epidemiological data and NFOI information via validated questionnaire. Noise hazard monitoring was executed by using Sound Level Meter (SLM) for environmental noise monitoring and Personal Sound Dosimeter for personal noise monitoring. Gathered data were analysed in quantitative method by using statistical software IBM SPSS Statistic version 21 and a risk matrix table for injury risk rating evaluation. It was discovered that high noise exposure level (≥ 85 dB[A]) was significantly associated with non-fatal occupational injury among OP workers (φ=0.123, p<0.05) with OR=1.87 (95% CI, 1.080-3.235, p<0.05). Risk rating for reported NFOI was at moderate level, with minor cuts and scratches were the dominant type of injury (42.6%). Analysis of logistic regression indicated that working in shift, not wearing protective gloves, health problems such as shortness of breath and ringing in ears, and excessive noise level (≥ 85 dB[A]) were the risk factors of NFOI in palm oil mills among OP workers. A framework of nonfatal injury surveillance in palm oil mills was developed based on the findings with integration of risk management process and injury prevention principles. This framework is anticipated to help the management in decision making for preventive actions and early detection of occupational health effects among workers

Design of a digital signal processing system on chip for an eddy current probe

In 1965 Gordon Moore, co-founder of Intel, observed that the number of transistors per square inch on integrated circuits had doubled every year since the integrated circuit was invented. Moore predicted that this trend would continue for the foreseeable future. In subsequent years, the pace slowed down, but data density has doubled approximately every 18 months, which is the current definition of Moore\u27s Law. The Semiconductor Industry Association roadmap derived from Moore\u27s Law promotes continuation of the decrease in minimum feature size and wafer size increase as the bases for the semiconductor industry\u27s successful future. This continuation of the decrease in minimum feature size and increase in wafer size has a number of important implications. One such important implication is that there will be an increase in chip manufacturing cost. This increase in die manufacturing cost has caused chip designers to investigate the implementation of single chip systems instead of the traditional design of multiple chip systems. The benefit of having a single chip system is that it can provide the same performance yet consume less space and power than multiple chip systems, which in turn cut manufacturing cost. The research conducted describes the design and implementation of an integrated circuit digital signal processing system for an eddy current probe. For this project a digital signal processing system that removes noisy signal components and amplifies the signal produced by an eddy current probe was designed. The purpose of this system is to have the ability to detect cracks in a material and to output that information to an ADC, which then is used to provide digital information to a computer for interpolation. In order to create a digital signal processing system capable of this, multiple building blocks are needed. This includes the design of a low pass filter, a variable gain amplifier which incorporates an operational amplifier and digital-to-analog converter, a current bias cell, and a shift register. An analysis and discussion of the design and fabricated integrated circuit in a TSMC 0.18 micron process is presented

Low-power switched capacitor voltage reference

Low-power analog design represents a developing technological trend as it emerges from a rather limited range of applications to a much wider arena affecting mainstream market segments. It especially affects portable electronics with respect to battery life, performance, and physical size. Meanwhile, low-power analog design enables technologies such as sensor networks and RFID. Research opportunities abound to exploit the potential of low power analog design, apply low-power to established fields, and explore new applications. The goal of this effort is to design a low-power reference circuit that delivers an accurate reference with very minimal power consumption. The circuit and device level low-power design techniques are suitable for a wide range of applications. To meet this goal, switched capacitor bandgap architecture was chosen. It is the most suitable for developing a systematic, and groundup, low-power design approach. In addition, the low-power analog cell library developed would facilitate building a more complex low-power system. A low-power switched capacitor bandgap was designed, fabricated, and fully tested. The bandgap generates a stable 0.6-V reference voltage, in both the discrete-time and continuous-time domain. The system was thoroughly tested and individual building blocks were characterized. The reference voltage is temperature stable, with less than a 100 ppm/°C drift, over a --60 dB power supply rejection, and below a 1 [Mu]A total supply current (excluding optional track-and-hold). Besides using it as a voltage reference, potential applications are also described using derivatives of this switched capacitor bandgap, specifically supply supervisory and on-chip thermal regulation

Theoretical Study of the Circuit Architecture of the Basic CFOA and Testing Techniques

This paper examines the closed-loop characteristics of the basic CFOA, and in particular, the dynamic response. Additionally, it also examines the design and advantages of the CFOA regarding its ability to provide a significantly constant closed-loop bandwidth for closed-loop voltage gain. Secondly, the almost limitless slew–rate provided by the class AB input stage that makes it superior to the VOA counterpart. Additionally; this paper also concerns the definitions and measurements of the terminal parameters of the CFOA, regarded as a ‘black box’. It does not deal with the way that these parameters are related to the properties of the active passive and active components of a particular circuit configuration. Simulation is used in terminal parameter determination: this brings with it the facility of using test conditions that would not normally prevail in a laboratory test on silicon implementations of the CFOAs. Thus, we can apply 1mA and 1mV test signals from, respectively, infinite and zero source impedances that range in frequency from d.c to some tens of GHz. Also, we assume the existence of resistors with identical Ohmic value and very high value ideal capacitors. Where appropriate, practical test methods are referred to physical laboratory prototypes