Analysis of design strategies for RF ESD problems in CMOS circuits

This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip

Characterization of triboelectric charging in data centers/display panel manufactures, and EMI visualization based on energy parcels method in high speed interconnections

This dissertation is composed of five papers. In the first three papers, triboelectric charging, which is the underlying cause of most electrostatic discharge (ESD), during daily human activities in data centers such as well-defined pattern walking, random walking, standing up from a chair, and taking off a sweater is investigated. Further, the effect of environmental condition (temperature and relative humidity), the footwear, and flooring material in building the static voltage and the discharge process are studied. In the fourth paper, triboelectric charge generation on the glass is investigated during the glass transportation by roller conveyor systems in display manufacturing. The underlying parameters that affect the static charging on both glass and rollers consisting of roller material, roller radius, transfer velocity, transfer acceleration, traveling distance, and relative humidity are explored. The fifth paper focuses on the shielding effectiveness (SE) of quad form-factor pluggable (QSFP) interconnections cages with heatsinks, which are often only optimized for thermal, mechanical, and volume manufacturing. Energy parcels and their trajectory concept are applied to electromagnetic waves (EM) to visualize the coupling paths in a QSFP cage with a rising heatsink. The rising heatsink creates a new coupling path for EM waves to leak to the cage and emit from the routers/switches chassis faceplate. An EMI mitigation technique is introduced and its performance is evaluated with SE measurement for the frequency of 1-40 GHz with and without the active operational of 40 Gbps optical module in a dual reverberation chamber --Abstract, page iv

Characterization of an Integrated Circuit with Respect to Electrostatic Discharge-Induced Soft Failures

This research proposal presents a methodology whereby an integrated circuit (IC) can be characterized with respect to soft-failures induced by Electrostatic Discharge (ESD)-like events. This methodology uses an exclusively black-box approach to determine the response of an IC in a system-level environment, thereby allowing it to be implemented without intimate knowledge of the DUT IC. Results from this methodology can be referenced during system design to raise awareness of specific vulnerabilities of the core system ICs. During work on this methodology, several sub topics have been explored and developed in the field of system-level ESD. Sections 2 and 3 introduce two topics which were developed to facilitate the generation and expression of IC pin models. Papers 1 and 2 introduce injection methods for characterizing complete systems on an interface-by-interface basis and form the foundation for the following works. Papers 2 and 3 mirror Papers 1 and 2 but instead shift focus away from the system as a whole and outline methods for characterizing the integrated circuits directly. Finally, Section 4 outlines a model method which can be used to describe the failures found in Paper 4 in circuit simulation, rounding out the work. Additional measurements which were unable to be included in Paper 4 are included in Appendices A, B, and C --Abstract, page iv

Investigating the effect of operating condition on ESD-induced soft-failures

Conflicting observations have been found in the literature regarding the effect of operating conditions on ESD (electrostatic discharge) susceptibility. While some studies have suggested a strong correlation between the two, others observed little to no correlation. In this work, a systematic study has been carried out suggesting the existence of a strong correlation between the ESD susceptibility and operating conditions. It is found that the root cause of this conflict is random ESD noise injection. A measurement approach is proposed to synchronize the noise injection with the system activity such as high/low CPU load. In this approach, the current consumption or the EMI (electromagnetic interference) of the device under test is monitored and used to synchronize the injections. To improve the poor repeatability of the ESD tests, the proposed approach is incorporated into a robotic scanner to create an automated ESD tester. Soft failure detection algorithms are added to the tester, giving it the ability to detect (and characterize) a soft failure in a similar way as a human - through sight and hearing. This is the first time that image processing algorithms are used for characterizing soft failures. Using the tester, a 2-D color-coded susceptibility map is obtained for each soft failure. These failure-specific maps can be used to identify/pinpoint the sensitive locations of the device knowing the soft failure type, reducing the tedious and time-consuming process of soft failure investigations --Abstract, page iv

System and IC level analysis of electrostatic discharge (ESD) and electrical fast transient (EFT) immunity and associated coupling mechanisms

The exposure of electronic circuits to lightning, electrostatic discharge (ESD), electrical fast transients (EFT) or sine wave signals can reveal RF immunity problems. Typical problems include temporary malfunctions or permanent damage of integrated circuits (ICs). In an effort to reproduce those disturbances, a series of electromagnetic compatibility standards has been developed. However, a complete understanding of the root cause of the immunity problems has yet to be established. This dissertation discusses immunity problems in three papers, starting at the system level, via the coupling path into the IC --Abstract, page iv

On-Chip ESD Protection Design: Optimized Clamps

The extensive use of Integrated Circuits (ICs) means complex working conditions for these tiny chips. To guarantee the ICs could work properly in various environments, some special protection strategies are required to improve the reliability of system. From all the possible reliability issues, the electrostatics discharge (ESD) might be the most common one. The peak current of electrostatics can be as high as tens of amperes and the peak voltage can be over thousand voltages. In contrast, the size of semiconductor device fabricated is continuing to scale down, making it even more vulnerable to high level overstress and current surge induced by ESD event. To protect the on-chip semiconductor from damage, some extra clamp cells are put together to consist a network. The network can redirect the superfluous current through the ESD network and clamp the voltage to a low level. In this dissertation, one design concept is introduced that uses the combination of some basic ESD devices to meet different requirements first, and then tries to establish parasitic current path among these devices to further increase the current handling capability. Some design cases are addressed to demonstrate this design concept is valid and efficient: 1. A combination of silicon-controlled-rectifier (SCR) and diode cluster is implemented to resolve the overshoot issue under fast ESD event. 2. A new SCR structure is introduced, which can be used as padding device to increase the clamping voltage without affecting other parameters. Based on this padding device, two design cases are introduced. 3. A controllable SCR clamp structure is presented, which has high current handling capability and can be controlled with by small signal. All these structures and topologies described in this dissertation are compatible with most of popular semiconductor fabrication process

Optimization of ESD Protection Methods in Electronics Assembly Based on Process and Product Specific Risks

The last 40 years has seen significant development in electrical component and system technologies. However, advances with semiconductor technologies, cost optimizations, and die area shrinking have made electronics more sensitive to excess electrical stress and electromagnetic disturbances. In this dissertation work, one of these stress scenarios is studied: electrostatic discharge (ESD) risks in the electronics assembly process environment. In the assembly process, single electrical components, circuit boards, and different subassemblies are assembled together, tested, and programmed to complete fully functional electrical products.A noncontrolled electronics assembly environment produces unpredictable ESD risks and causes yield losses. Therefore, it is necessary to protect electronics against ESD during handling and manufacturing. This is accomplished with the aid of an electrostatic protected area (EPA) and an ESD control program plan, which are typically built according to IEC61340-5-1-2007 and ANSI S20.20-2014 standards. These two standards define how to design, establish, implement, and maintain the program with administrative and technical requirements. Here, a 100 V human body model (HBM) limit is currently used as the base for building EPAs and ESD control programs. However, current ESD control programs are not always able to prevent ESD damages in EPA. On top of actual ESD events, there can be electromagnetic interference (EMI) initiated product and equipment disturbances in well-built EPAs.In this research work, the main focus is on additional ESD control methods that go beyond the specifications and requirements of the IEC61340-5-1 and ANSI/ESD S20.20 standards. The objective is to optimize ESD protection methods based on real ESD risk scenarios found during PCB assembly, testing, handling, and during system final assembly to achieve close to zero-failure level. At the same time, the objective is to optimize ESD control-related costs in the process area.Based on the research, the focus of the additional ESD and EMI control methods should be with final assembly, programming, and testing process phases where about 90% observed failure and disturbance cases have occurred. Therefore, in an improved ESD control program, EMI control, controlling product part and cable charging are added into the program, together with groundings and other basic controlled EPA items. The charging of product parts should be monitored with potential, discharge current and charge meters, and that data should be used together with process analysis to detect all known ESD risk scenarios. The sensitivity of subassemblies should be tested, for example, by using a charged board event (CBE), field collapse event (FCE), and cable discharge event (CDE) methods that simulate real world ESD scenarios found in the process area. This gives more accurate data for risk assessments than an electrical-component-specific HBM or charged device model (CDM) qualification data.The proposed additional control methods were implemented in more than 10 large electronics assembly facilities, resulting in a significant reduction in ESD-related failures and disturbance-related process yield challenges. Therefore, as a future work, product and process specific ESD and EMI risk should be emphasized in ESDcontrol-related trainings, standards, standard practices, and technical reports

Bowdoin College Course Guide (2016-2017)

https://digitalcommons.bowdoin.edu/course-catalogues/1299/thumbnail.jp

Bowdoin College Catalogue and Academic Handbook (2019-2020)

https://digitalcommons.bowdoin.edu/course-catalogues/1304/thumbnail.jp

Design And Characterization Of Noveldevices For New Generation Of Electrostaticdischarge (esd) Protection Structures

The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications\u27 performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement