Women in circuits and systems (WiCAS) and young professionals (YP) at ICECS 2020.

A 'Women in Circuits and Systems' (WiCAS) event and a 'Young Professionals' (YP) event took place during the 27th Institute of Electrical and Electronics Engineers (IEEE) International conference on electronics circuits and systems (ICECS), the flagship conference for the Region 8 of the IEEE Circuits and Systems Society (CASS). The WiCAS events traditionally aim to inspire and motivate both students and young professionals in the domain of circuits and systems to have efficient roles in their professions, by meeting successful female engineers and professors, through interesting technical and professional talks in fields of interest of CASS. The YP events usually include start-ups presentation, poster and demo sessions, aiming to provide a thrilling environment for early career researchers to present their work. Joining this event, young professionals have the opportunity to learn about state of the art and most advanced activities in the area of circuits and systems, meet and interact with their peers, receive feedback from internationally well-known experts in the CASS domain from both academia and industry

Optimized Implementation of Memristor-Based Full Adder by Material Implication Logic

Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors are also applied in logic circuit design. Material implication logic is one of the main areas with memristors. In this paper an optimized memristor-based full adder design by material implication logic is presented. This design needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders. Also the presented full adder needs only 184 computational steps which enhance former full adder design speed by 20 percent.Comment: International Conference on Electronics Circuits and Systems (ICECS), 201

Design of a Quasi-Linear Rail-to-Rail Delay Element with an Extended Programmable Range

peer-reviewe

Very Low Cost Entropy Source Based on Chaotic Dynamics Retrofittable on Networked Devices to Prevent RNG Attacks

Good quality entropy sources are indispensable in most modern cryptographic protocols. Unfortunately, many currently deployed networked devices do not include them and may be vulnerable to Random Number Generator (RNG) attacks. Since most of these systems allow firmware upgrades and have serial communication facilities, the potential for retrofitting them with secure hardware-based entropy sources exists. To this aim, very low-cost, robust, easy to deploy solutions are required. Here, a retrofittable, sub 10$ entropy source based on chaotic dynamics is illustrated, capable of a 32 kbit/s rate or more and offering multiple serial communication options including USB, I2C, SPI or USART. Operation is based on a loop built around the Analog to Digital Converter (ADC) hosted on a standard microcontroller.Comment: 4 pages, 6 figures. Pre-print from conference proceedings; IEEE 21th International Conference on Electronics, Circuits, and Systems (ICECS 2014), pp. 175-178, Dec. 201

Time-Precision Flexible Adder

Paper submitted to 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sharjah, Emiratos Árabes, 2003.A new conception of flexible calculation that allows us to adjust a sum depending on the available time computation is presented. More specifically, the objective is to obtain a calculation model that makes the processing time/precision more flexible. The addition method is based on carry-select scheme adder and the proposed design uses precalculated data stored in look-up tables, which provide, above all, quality results and systematization in the implementation of low level primitives that set parameters for the processing time. We report an evaluation of the architecture in area, delay and computation error, as well as a suitable implementation in FPGA to validate the design.This work is being backed by grant DPI2002-04434-C04-01 from the Ministerio de Ciencia y Tecnología of the Spanish Government

RTD based logic circuits using generalized threshold gates

Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e. these circuits are built from threshold gates (TGs). The MOBILE realization of generalized threshold gates is being investigated. Multi-Threshold Threshold Gates (MTTGs) have been proposed which further increase the functionality of the original TGs. Recently, we have proposed a novel MOBILE circuit topology obtained by fundamental properties of threshold functions. This paper describes the design of n-bit adders using these novel MOBILE circuit topologies. A comparison with designs based on TGs and MTTGs is carried out showing advantages in terms of speed and power delay product and device counts.España, Gobierno TEC2007-67245Junta de Andalucía EXC/2007/TIC-296