End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

Study of Interfacial Crack Propagation in Flip Chip Assemblies with Nano-filled Underfill Materials

No-flow underfill materials that cure during the solder reflow process is a relatively new technology. Although there are several advantages in terms of cost, time and processing ease, there are several reliability challenges associated with no-flow underfills. When micron-sized filler particles are introduced in no-flow underfills to enhance the solder bump reliability, such filler particles could prevent the solder bumps making reliable electrical contacts with the substrate pads during solder reflow, and therefore, the assembly yield would be adversely affected. The use of nano-sized filler particles can potentially improve assembly yield while offering the advantages associated with filled underfill materials. The objective of this thesis is to study the thermo-mechanical reliability of nano-filled epoxy underfills (NFU) through experiments and theoretical modeling. In this work, the thermo-mechanical properties of NFUs with 20-nm filler particles have been measured. An innovative residual stress test method has been developed to measure the interfacial fracture toughness. Using the developed residual stress method and the single-leg bending test, the mode-mixity-dependent fracture toughness for NFU-SiN interface has been determined. In addition to such monotonic interfacial fracture characterization, the interface crack propagation under thermo-mechanical fatigue loading has been experimentally characterized, and a model for fatigue interface crack propagation has been developed. A test vehicle comprising of several flip chips was assembled using the NFU material and the reliability of the flip-chip assemblies was assessed under thermal shock cycles between -40oC and 125oC. The NFU-SiN interfacial delamination propagation and the solder bump reliability were monitored. In parallel, numerical models were developed to study the interfacial delamination propagation in the flip chip assembly using conventional interfacial fracture mechanics as well as cohesive zone modeling. Predictions for interfacial delamination propagation using the two approaches have been compared. Based on the theoretical models and the experimental data, guidelines for design of NFUs against interfacial delamination have been developed.Ph.D.Committee Chair: Sitaraman, Suresh; Committee Member: Qu, Jianmin; Committee Member: Tonapi, Sandeep; Committee Member: Tummala, Rao; Committee Member: Ume, Charles; Committee Member: White, Georg

Structural Design and Optimization of 65nm Cu/low-k Flipchip Package

Master'sMASTER OF ENGINEERIN

Fiabilité de l’underfill et estimation de la durée de vie d’assemblages microélectroniques

Abstract : In order to protect the interconnections in flip-chip packages, an underfill material layer is used to fill the volumes and provide mechanical support between the silicon chip and the substrate. Due to the chip corner geometry and the mismatch of coefficient of thermal expansion (CTE), the underfill suffers from a stress concentration at the chip corners when the temperature is lower than the curing temperature. This stress concentration leads to subsequent mechanical failures in flip-chip packages, such as chip-underfill interfacial delamination and underfill cracking. Local stresses and strains are the most important parameters for understanding the mechanism of underfill failures. As a result, the industry currently relies on the finite element method (FEM) to calculate the stress components, but the FEM may not be accurate enough compared to the actual stresses in underfill. FEM simulations require a careful consideration of important geometrical details and material properties. This thesis proposes a modeling approach that can accurately estimate the underfill delamination areas and crack trajectories, with the following three objectives. The first objective was to develop an experimental technique capable of measuring underfill deformations around the chip corner region. This technique combined confocal microscopy and the digital image correlation (DIC) method to enable tri-dimensional strain measurements at different temperatures, and was named the confocal-DIC technique. This techique was first validated by a theoretical analysis on thermal strains. In a test component similar to a flip-chip package, the strain distribution obtained by the FEM model was in good agreement with the results measured by the confocal-DIC technique, with relative errors less than 20% at chip corners. Then, the second objective was to measure the strain near a crack in underfills. Artificial cracks with lengths of 160 μm and 640 μm were fabricated from the chip corner along the 45° diagonal direction. The confocal-DIC-measured maximum hoop strains and first principal strains were located at the crack front area for both the 160 μm and 640 μm cracks. A crack model was developed using the extended finite element method (XFEM), and the strain distribution in the simulation had the same trend as the experimental results. The distribution of hoop strains were in good agreement with the measured values, when the model element size was smaller than 22 μm to capture the strong strain gradient near the crack tip. The third objective was to propose a modeling approach for underfill delamination and cracking with the effects of manufacturing variables. A deep thermal cycling test was performed on 13 test cells to obtain the reference chip-underfill delamination areas and crack profiles. An artificial neural network (ANN) was trained to relate the effects of manufacturing variables and the number of cycles to first delamination of each cell. The predicted numbers of cycles for all 6 cells in the test dataset were located in the intervals of experimental observations. The growth of delamination was carried out on FEM by evaluating the strain energy amplitude at the interface elements between the chip and underfill. For 5 out of 6 cells in validation, the delamination growth model was consistent with the experimental observations. The cracks in bulk underfill were modelled by XFEM without predefined paths. The directions of edge cracks were in good agreement with the experimental observations, with an error of less than 2.5°. This approach met the goal of the thesis of estimating the underfill initial delamination, areas of delamination and crack paths in actual industrial flip-chip assemblies.Afin de protéger les interconnexions dans les assemblages, une couche de matériau d’underfill est utilisée pour remplir le volume et fournir un support mécanique entre la puce de silicium et le substrat. En raison de la géométrie du coin de puce et de l’écart du coefficient de dilatation thermique (CTE), l’underfill souffre d’une concentration de contraintes dans les coins lorsque la température est inférieure à la température de cuisson. Cette concentration de contraintes conduit à des défaillances mécaniques dans les encapsulations de flip-chip, telles que la délamination interfaciale puce-underfill et la fissuration d’underfill. Les contraintes et déformations locales sont les paramètres les plus importants pour comprendre le mécanisme des ruptures de l’underfill. En conséquent, l’industrie utilise actuellement la méthode des éléments finis (EF) pour calculer les composantes de la contrainte, qui ne sont pas assez précises par rapport aux contraintes actuelles dans l’underfill. Ces simulations nécessitent un examen minutieux de détails géométriques importants et des propriétés des matériaux. Cette thèse vise à proposer une approche de modélisation permettant d’estimer avec précision les zones de délamination et les trajectoires des fissures dans l’underfill, avec les trois objectifs suivants. Le premier objectif est de mettre au point une technique expérimentale capable de mesurer la déformation de l’underfill dans la région du coin de puce. Cette technique, combine la microscopie confocale et la méthode de corrélation des images numériques (DIC) pour permettre des mesures tridimensionnelles des déformations à différentes températures, et a été nommée le technique confocale-DIC. Cette technique a d’abord été validée par une analyse théorique en déformation thermique. Dans un échantillon similaire à un flip-chip, la distribution de la déformation obtenues par le modèle EF était en bon accord avec les résultats de la technique confocal-DIC, avec des erreurs relatives inférieures à 20% au coin de puce. Ensuite, le second objectif est de mesurer la déformation autour d’une fissure dans l’underfill. Des fissures artificielles d’une longueuer de 160 μm et 640 μm ont été fabriquées dans l’underfill vers la direction diagonale de 45°. Les déformations circonférentielles maximales et principale maximale étaient situées aux pointes des fissures correspondantes. Un modèle de fissure a été développé en utilisant la méthode des éléments finis étendue (XFEM), et la distribution des contraintes dans la simuation a montré la même tendance que les résultats expérimentaux. La distribution des déformations circonférentielles maximales était en bon accord avec les valeurs mesurées lorsque la taille des éléments était plus petite que 22 μm, assez petit pour capturer le grand gradient de déformation près de la pointe de fissure. Le troisième objectif était d’apporter une approche de modélisation de la délamination et de la fissuration de l’underfill avec les effets des variables de fabrication. Un test de cyclage thermique a d’abord été effectué sur 13 cellules pour obtenir les zones délaminées entre la puce et l’underfill, et les profils de fissures dans l’underfill, comme référence. Un réseau neuronal artificiel (ANN) a été formé pour établir une liaison entre les effets des variables de fabrication et le nombre de cycles à la délamination pour chaque cellule. Les nombres de cycles prédits pour les 6 cellules de l’ensemble de test étaient situés dans les intervalles d’observations expérimentaux. La croissance de la délamination a été réalisée par l’EF en évaluant l’énergie de la déformation au niveau des éléments interfaciaux entre la puce et l’underfill. Pour 5 des 6 cellules de la validation, le modèle de croissance du délaminage était conforme aux observations expérimentales. Les fissures dans l’underfill ont été modélisées par XFEM sans chemins prédéfinis. Les directions des fissures de bord étaient en bon accord avec les observations expérimentales, avec une erreur inférieure à 2,5°. Cette approche a répondu à la problématique qui consiste à estimer l’initiation des délamination, les zones de délamination et les trajectoires de fissures dans l’underfill pour des flip-chips industriels

Thermomechanical fatigue failure of interfaces in lead-free solders

The European Union Waste Electrical and Electronic Equipment Directive (WEEE) and Restriction of Hazardous Substances Directive (RoHS) banned lead from electronic systems from July 1, 2006 onwards, which has led to much interest in leadfree solders in the past years. Among several lead-free solder alternatives, SnAgCu is a widely accepted replacement due to its better creep-fatigue resistance and microstructural stability. SnAgCu has been extensively studied in the past decade, however, there are still issues to be resolved concerning solder reliability, the underlying mechanisms of thermo-mechanical fatigue failure, fatigue life predictions and the overall effect of decreasing component size, driven by the ongoing miniaturization trend. This thesis aims to scientifically contribute to this subject by a coupled experimental-numerical approach. In solder joint reliability, the bump/pad interface has a crucial role, the quality of which is determined by the metallization and interfacial defects. Solder balls, solder paste and cast eutectic SnAgCu are reflowed on Cu, Ni/Au and Cu/Ni(V)/Au metallization layers and the substrate influence on the bulk and interfacial metallurgy is examined. The damage propagation at SnAgCu soldered joints on Cu and Ni/Au substrates are investigated and microstructure related damage localization is identified as the dominant failure mechanism. Therefore, continuum damage approaches are believed to be inadequate for solder joint reliability predictions. Nano-indentation and tensile testing is used for the mechanical characterization of SnAgCu. An assessment on indentation parameters for solders is conducted and the influence of the Ag content on material properties of SnAgCu is presented. One of the main causes of ball grid array (BGA) failure is thermo-mechanical fatigue crack propagation in the solder, which is almost always observed at the bump/pad junction. Motivated by this fact, a combined experimental-numerical study on the cyclic mechanical response of SnAgCu/Ni-Au interface is conducted. In this study, damage evolution at the bond/pad interface is characterized by dedicated fatigue tests. Local deformations leading to crack propagation are simulated by separation of interfaces through a cohesive zone approach. Solder joints are tested under cyclic shear and cyclic tension for different specimen sizes and strain amplitudes. Two different damagemechanisms are observed: local deformations in the bulk and at the bonding interface. The interfacial failure mode is typically favored at a high initial stress, and a small solder volume. Crack propagation is simulated by an irreversible linear traction-separation cohesive zone law accompanied by a non-linear interfacial damage parameter. Later, tensile and shear experiments are used to characterize the cohesive zone parameters for the normal and the tangential opening, respectively. Interfacial fatigue damage in BGA solders is caused by the difference in coefficient of thermal expansion (CTE) of the materials in the package. Apart from this thermal incompatibility in the package, Sn based solders are themselves prone to thermal fatigue damage due to the intrinsic thermal anisotropy of the ß-Sn phase. Thermal fatigue causes local deformations especially at the grain boundaries. Hence, the thermal fatigue response of bulk SnAgCu is investigated as well. Bulk SnAgCu specimens are thermally cycled between -40 and 125¿C and mechanically tested afterwards in order to quantify the thermal fatigue damage. A size dependent cyclic softening behavior is observed. Test specimens are individually modeled including the microstructure and local crystallographic orientations, on the basis of orientation imaging scans (OIM). Both thermal cycling and tensile testing are imposed as boundary conditions. Reproducing the experimental results in the simulations, parameters of a cohesive zone based intergranular fatigue damagemodel are identified. Finally, the intergranular damage law characterized in this study is combined with the bump/pad interfacial damage law, and a 2Dmicrostructure-incorporated fatigue life prediction tool is established. Using this tool, it is shown that the failure mode of a soldered joint depends extensively on its geometry. The model presented above is extended to 3D for a more complete description of the problem. To provide the microstructural input, a database containing OIM scans of several SnAgCu solder balls is constructed. A missing constituent in the model so far, interfacial defects, i.e. voids, are examined statistically using newly manufactured BGA packages, revealing information on their size, position and frequency. Combining all the data collected, i.e. material properties, microstructure, defects, local damage laws, a 3D slice model from a BGA package is constructed. The slice model contains a single solder ball connecting the board and the chip. A series of case studies is created using experimental input such as different microstructures and initial defects allowing a statistical analysis. Fatigue life of these models are predicted and the results are validated by failure distribution analyses of BGA packages provided by the industry. Here the critical solder ball assumption is made: if a solder ball fails, the electrical circuit of the BGA package is open, thus the package fails. Setting a critical damage value for the interfaces accumulating fatigue damage, a good agreement with the experiments and simulations is obtained. It is seen that microstructural modeling allows to predict and understand the scatter in the solder ball fatigue life observed in reality. Finally, the effect of solder ball size and geometry on interconnect reliability is dis cussed on the basis of numerical analyses. For this purpose, a geometry factor and a microstructure factor is defined, and their influence on damage evolution is discusse

Thermomechanical fatigue failure of interfaces in lead-free solders

The European Union Waste Electrical and Electronic Equipment Directive (WEEE) and Restriction of Hazardous Substances Directive (RoHS) banned lead from electronic systems from July 1, 2006 onwards, which has led to much interest in leadfree solders in the past years. Among several lead-free solder alternatives, SnAgCu is a widely accepted replacement due to its better creep-fatigue resistance and microstructural stability. SnAgCu has been extensively studied in the past decade, however, there are still issues to be resolved concerning solder reliability, the underlying mechanisms of thermo-mechanical fatigue failure, fatigue life predictions and the overall effect of decreasing component size, driven by the ongoing miniaturization trend. This thesis aims to scientifically contribute to this subject by a coupled experimental-numerical approach. In solder joint reliability, the bump/pad interface has a crucial role, the quality of which is determined by the metallization and interfacial defects. Solder balls, solder paste and cast eutectic SnAgCu are reflowed on Cu, Ni/Au and Cu/Ni(V)/Au metallization layers and the substrate influence on the bulk and interfacial metallurgy is examined. The damage propagation at SnAgCu soldered joints on Cu and Ni/Au substrates are investigated and microstructure related damage localization is identified as the dominant failure mechanism. Therefore, continuum damage approaches are believed to be inadequate for solder joint reliability predictions. Nano-indentation and tensile testing is used for the mechanical characterization of SnAgCu. An assessment on indentation parameters for solders is conducted and the influence of the Ag content on material properties of SnAgCu is presented. One of the main causes of ball grid array (BGA) failure is thermo-mechanical fatigue crack propagation in the solder, which is almost always observed at the bump/pad junction. Motivated by this fact, a combined experimental-numerical study on the cyclic mechanical response of SnAgCu/Ni-Au interface is conducted. In this study, damage evolution at the bond/pad interface is characterized by dedicated fatigue tests. Local deformations leading to crack propagation are simulated by separation of interfaces through a cohesive zone approach. Solder joints are tested under cyclic shear and cyclic tension for different specimen sizes and strain amplitudes. Two different damagemechanisms are observed: local deformations in the bulk and at the bonding interface. The interfacial failure mode is typically favored at a high initial stress, and a small solder volume. Crack propagation is simulated by an irreversible linear traction-separation cohesive zone law accompanied by a non-linear interfacial damage parameter. Later, tensile and shear experiments are used to characterize the cohesive zone parameters for the normal and the tangential opening, respectively. Interfacial fatigue damage in BGA solders is caused by the difference in coefficient of thermal expansion (CTE) of the materials in the package. Apart from this thermal incompatibility in the package, Sn based solders are themselves prone to thermal fatigue damage due to the intrinsic thermal anisotropy of the ß-Sn phase. Thermal fatigue causes local deformations especially at the grain boundaries. Hence, the thermal fatigue response of bulk SnAgCu is investigated as well. Bulk SnAgCu specimens are thermally cycled between -40 and 125¿C and mechanically tested afterwards in order to quantify the thermal fatigue damage. A size dependent cyclic softening behavior is observed. Test specimens are individually modeled including the microstructure and local crystallographic orientations, on the basis of orientation imaging scans (OIM). Both thermal cycling and tensile testing are imposed as boundary conditions. Reproducing the experimental results in the simulations, parameters of a cohesive zone based intergranular fatigue damagemodel are identified. Finally, the intergranular damage law characterized in this study is combined with the bump/pad interfacial damage law, and a 2Dmicrostructure-incorporated fatigue life prediction tool is established. Using this tool, it is shown that the failure mode of a soldered joint depends extensively on its geometry. The model presented above is extended to 3D for a more complete description of the problem. To provide the microstructural input, a database containing OIM scans of several SnAgCu solder balls is constructed. A missing constituent in the model so far, interfacial defects, i.e. voids, are examined statistically using newly manufactured BGA packages, revealing information on their size, position and frequency. Combining all the data collected, i.e. material properties, microstructure, defects, local damage laws, a 3D slice model from a BGA package is constructed. The slice model contains a single solder ball connecting the board and the chip. A series of case studies is created using experimental input such as different microstructures and initial defects allowing a statistical analysis. Fatigue life of these models are predicted and the results are validated by failure distribution analyses of BGA packages provided by the industry. Here the critical solder ball assumption is made: if a solder ball fails, the electrical circuit of the BGA package is open, thus the package fails. Setting a critical damage value for the interfaces accumulating fatigue damage, a good agreement with the experiments and simulations is obtained. It is seen that microstructural modeling allows to predict and understand the scatter in the solder ball fatigue life observed in reality. Finally, the effect of solder ball size and geometry on interconnect reliability is dis cussed on the basis of numerical analyses. For this purpose, a geometry factor and a microstructure factor is defined, and their influence on damage evolution is discusse

Thermal and thermo-mechanical performance of voided lead-free solder thermal interface materials for chip-scale packaged power device

The need to maximise thermal performance of electronic devices coupled with the continuing trends on miniaturization of electronic packages require innovative package designs for power devices and modules such as Electronic Control Unit (ECU). Chip scale packaging (CSP) technology offer promising solution for packaging power electronics. This is as a result of the technology’s relatively improved thermal performance and inherent size advantage. In CSP technology, heat removal from the device could be enhanced through the backside of the chip. Heat dissipating units such as heat spreader and/or heat sink can be attached to the backside (reverse side) of the heat generating silicon die (via TIM) in an effort to improve the surface area available for heat dissipation. TIMs are used to mechanically couple the heat generating chip to a heat sinking device and more crucially to enhance thermal transfer across the interface. Extensive review shows that solder thermal interface materials (STIMs) apparently offer better thermal performance than comparable state-of-the-art commercial polymer-based TIMs and thus a preferable choice in packaging power devices. Nonetheless, voiding remains a major reliability concern of STIMs. This is coupled with the fact that solder joints are generally prone to fatigue failures under thermal cyclic loading. Unfortunately, the occurrence of solder voids is almost unavoidable during manufacturing process and is even predominant in lead (Pb)-free solder joints. The impacts of these voids on the thermal and mechanical performance of solder joints are not clearly understood and scarcely available in literature especially with regards to STIMs (large area solder joints). Hence, this work aims to investigate STIM and the influence of voids on the thermo-mechanical and thermal performance of STIM. As previous results suggest that factors such as the location, configuration (spatial arrangement) and size of voids play vital roles on the exact effect of voids, extensive three dimensional (3D) finite element modelling is employed to elucidate the precise effect of these void features on a Pb-free STIM selected after thermo-mechanical fatigue test of standard Pb-free solder alloys. Finite element analysis (FEA) results show that solder voids configuration, size and location are all vital parameters in evaluating the mechanical and thermal impacts of voids. Depending on the location, configuration and size of voids; solder voids can either influence the initiation or propagation of damage in the STIM layer or the location of hot spot on the heat generating chip. Experimental techniques are further employed to compare and correlate levels of voiding and shear strength for representative Pb-free solders. Experimental results also suggest that void size, location and configuration may have an influence on the mechanical durability of solder joints. The findings of this research work would be of interest to electronic packaging engineers especially in the automotive sector and have been disseminated through publications in peer reviewed journals and presentations in international conferences

Dynamic Mechanical and Failure Properties of Solder Joints

Ph.DDOCTOR OF PHILOSOPH

Compliant copper microwire arrays for reliable interconnections between large low-CTE packages and printed wiring board

The trend to high I/O density, performance and miniaturization at low cost is driving the industry towards shrinking interposer design rules, requiring a new set of packaging technologies. Low-CTE packages from silicon, glass and low-CTE organic substrates enable high interconnection density, high reliability and integration of system components. However, the large CTE mismatch between the package and the board presents reliability challenges for the board-level interconnections. Novel stress-relief structures that can meet reliability requirements along with electrical performance while meeting the cost constraints are needed to address these challenges. This thesis focuses on a comprehensive methodology starting with modeling, design, fabrication and characterization to validate such stress-relief structures. This study specifically explores SMT-compatible stress-relief microwire arrays in thin polymer carriers as a unique and low-cost solution for reliable board-level interconnections between large low-CTE packages and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled in between the interposer and printed wiring board (PWB) as stress-relief interlayers. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. The models were built in 2.5D geometries to study the reliability of 400 µm-pitch interconnections with a 100 µm thick, 20 mm × 20 mm silicon package that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared to that of ball grid array (BGA) interconnections, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of microwire arrays. Copper microwires with 12 µm diameter and 50 µm height were fabricated on both sides of a 50 µm thick, thermoplastic polymer carrier using dryfilm based photolithography and bottom-up electrolytic plating. The copper microwire interconnections were assembled between silicon interposer and FR-4 PWB through SMT-compatible process. Thermal mechanical reliability of the interconnections was characterized by thermal cycling test from -40°C to 125°C. The initial fatigue failure in the interconnections was identified at 700 cycles in the solder on the silicon package side, which is consistent with the modeling results. This study therefore demonstrated a highly-reliable and SMT-compatible solution for board-level interconnections between large low-CTE packages and printed wiring board.Ph.D