Interconnect reliability dependence on fast diffusivity paths

a b s t r a c t The reliability of interconnects in modern integrated circuits is determined by the magnitude and direction of the effective valence for electromigration (EM). The effective valence depends on local atomistic configurations of fast diffusivity paths such as metal interfaces, dislocations, and the grain boundary; therefore, microstructural variations lead to a statistically predictable behavior for the EM life time. Quantum mechanical investigations of EM have been carried out on an atomistic level in order to obtain numerically efficient methods for calculating the effective valence. The results of ab initio calculations of the effective valence have been used to parametrize the continuum-level EM models. The impact of fast diffusivity paths on the long term EM behavior is demonstrated with these models

Diffusivity variation in electromigration failure

Electromigration driven void dynamics plays an important role in the reliability of copper interconnects; a proper understanding of which is made more difficult due to local variations in line microstructure. In simulations, the parameter incorporating these variations best is the effective atomic diffusivity Deff which is sensitive to grain size and orientation, interface layer thickness, etc. We examine a number of experimental results and conclude that, to explain observations using current theoretical models, Deff values must vary significantly along the interconnect, and that such variations are enough to yield encouraging simulations of resistance variations under bidirectional stress

Effects of scaling on microstructure evolution of Cu nanolines and impact on electromigration reliability

textScaling can significantly degrade the electromigration (EM) lifetime for Cu interconnects, raising serious reliability concerns. Different methods have emerged to enhance the EM resistance of Cu by suppressing the interface diffusion (the historically fastest diffusion path), notably using CoWP metal cap and Mn alloying. With further scaling of Cu interconnects, EM reliability becomes increasingly complex due to changes in Cu microstructure. In ultra-fine Cu lines a large population of small grains mix with bamboo-type grains, resulting in an additional contribution of grain boundary diffusion to EM degradation. With the interface diffusion suppressed by CoWP or Mn alloying, the grain structure effect becomes even more important. The objective of this study is to investigate the EM reliability of ultra-fine Cu interconnects, focusing on the scaling effect on grain structure and mass transport. First, the detailed microstructure information of Cu interconnects down to the 22 nm node was analyzed using a transmission electron microscope (TEM)-based high resolution diffraction technique. A dominant sidewall growth of {111} grains was observed for 70 nm Cu lines (45 nm node), reflecting the importance of interfacial energy in controlling grain growth. The strength of the {111} texture was found to significantly increase as line width was reduced to 40 nm (22 nm node), while the length fraction of coherent twin boundaries was reduced to ~1%. Secondly, the results from microstructure together with the deduced interfacial and grain boundary diffusivities were used to identify flux divergent sites for void formation and to analyze the grain structure effect on EM statistics using a microstructure-based kinetic model. Finally, based on the analysis of Cu grain structure evolution with downscaling, the scaling behavior of EM drift velocity was investigated for Cu interconnects with CoWP capping and Mn alloying. This enables us to project the EM lifetime and statistics for future technology nodes. The Mn alloying effect on mass transport in combination of grain structure control was found to provide an effective means to improve EM reliability especially with further scaling. In summary, this study establishes a correlation between the microstructure of Cu nanolines, void formation kinetics, and EM statistics.Mechanical Engineerin

Study of initial void formation and electron wind force for scaling effects on electromigration in Cu interconnects

textThe continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes.Physic

차세대 반도체 배선을 위한 코발트 합금 자가형성 확산방지막 재료 설계 및 전기적 신뢰성에 대한 연구

학위논문(박사) -- 서울대학교대학원 : 공과대학 재료공학부, 2022.2. 주영창.Recently, the resistance-capacitance (RC) delay of the Cu interconnects in metal 1 (M1) level has been increased rapidly due to the reduction of the interconnect linewidth along with the transistor scaling down, and the interconnect reliability becomes a severe issue again. In order to overcome interconnect performance problems and move forward to the next-generation interconnects system, study on low resistivity (ρo) and low electron mean free path (λ) metals was conducted. Generally, metals such as Cobalt (Co), Ruthenium (Ru), and Molybdenum (Mo) are mentioned as candidates for next-generation interconnect materials, and since they have a low ρo × λ value, it is expected that the influence of interface scatterings and surface scattering can be minimized. However, harsh operating environments such as high electric fields, critical Joule heating, and reduction of the pitch size are severely deteriorating the performance of electronic devices as well as device reliability. For example, since time dependent dielectric breakdown (TDDB) problems for next-generation interconnect system have been reported recently, it is necessary to study alternative barrier materials and processes to improve the interconnect reliability. Specifically, extrinsic dielectric breakdown due to penetration of Co metal ions in high electric fields has been reported as a reliability problem to be solved in Co interconnect systems. Therefore, there is a need for new material system design and research on a robust diffusion barrier that prevents metal ions from penetrating into the dielectric, thereby improving the reliability of Co interconnects. Moreover, in order to lower the resistance of the interconnect, it is necessary to develop an ultra-thin barrier. This is because even a barrier with good reliability characteristics will degrade chip performance if it takes up a lot of volume in the interconnect. The recommended thickness for a single diffusion barrier layer is currently reported to be less than 2.5 nm. As a result, it is essential to develop materials that comprehensively consider performance and reliability. In this study, we designed a Co alloy self-forming barrier (SFB) material that can make sure of low resistance and high reliability for Co interconnects, which is attracting attention as a next-generation interconnect system. The self-forming barrier methodology induces diffusion of an alloy dopant at the interface between the metal and the dielectric during the annealing process. And the diffused dopant reacts with the dielectric to form an ultra-thin diffusion barrier. Through this methodology, it is possible to improve reliability by preventing the movement of metal ions. First of all, material design rules were established to screen the appropriate alloy dopants and all CMOS-compatible metals were investigated. Dopant resistivity, intermetallic compound formation, solubility in Co, activity coefficient in Co, and oxidation tendency is considered as the criteria for the dopant to escape from the Co matrix and react at the Co/SiO2 interface. In addition, thermodynamic calculations were performed to predict which phases would be formed after the annealing process. Based on thermodynamic calculations, 5 dopant metals were selected, prioritized for self-forming behavior. And the self-forming material was finally selected through thin film and device analysis. We confirmed that Cr, Zn, and Mn out-diffused to the surface of the thin film structure using X-ray photoelectron spectroscopy (XPS) depth profile and investigated the chemical state of out-diffused dopants through the analysis of a binding energy. Cr shows the most ideal self-forming behavior with the SiO2 dielectric and reacted with oxygen to form a Cr2O3 barrier. In metal-insulator-semiconductor (MIS) structure, out-diffused Cr reacts with SiO2 at the interface and forms a self-formed single layer. It was confirmed that the thickness of the diffusion barrier layer is about 1.2 nm, which is an ultra-thin layer capable of minimizing the total effective resistance. Through voltage-ramping dielectric breakdown (VRDB) tests, Co-Cr alloy showed highest breakdown voltage (VBD) up to 200 % than pure Co. The effect of Cr doping concentration and heat treatment condition applicable to the interconnect process was confirmed. When Cr was doped less than 1 at%, the robust electrical reliability was exhibited. Also, it was found that a Cr2O3 interfacial layer was formed when annealing process was performed at 250 °C or higher for 30 minutes or longer. In other words, Co-Cr alloy is well suited for the interconnect process because current interconnect process temperature is below 400 °C. And when the film thickness was lowered from 150 nm to 20 nm, excellent VBD values were confirmed even at high Cr doping concentration (~7.5 at%). It seems that the amount of Cr present at the Co/SiO2 interface plays a very important role in improving the Cr oxide SFB quality. Physical modeling is necessary to understand the amount of Cr at the interface according to the interconnect volumes and the reliability of the Cr oxide self-forming barrier. TDDB lifetime test also performed and Co-Cr alloy interconnect shows a highly reliable diffusion barrier property of self-formed interfacial layer. The DFT analysis also confirmed that Cr2O3 is a very promising barrier material because it showed a higher energy barrier value than the TiN diffusion barrier currently being studied. A Co-based self-forming barrier was designed through thermodynamic calculations that take performance and reliability into account in interconnect material system. A Co interconnect system with an ultra-thin Cr2O3 diffusion barrier with excellent reliability is proposed. Through this design, it is expected that high-performance interconnects based on robust reliability in the advanced interconnect can be implemented in the near future.최근 반도체 소자 스케일링에 따른 배선 선폭 감소로 M0, M1영역에서의 metal 비저항이 급격히 증가하여 배선에서의 RC delay가 다시 한번 크게 문제가 되고 있다. 이를 해결하기 위해서 차세대 배선 시스템에서는 낮은 비저항과 electron mean free path (EMFP)을 가지는 물질 연구가 진행되었다. 대표적으로 Co, Ru, Mo와 같은 금속들이 차세대 배선 재료 후보로 언급되고 있으며 낮은 ρ0 × λ 값을 갖기 때문에 interface (surface) scattering과 grain boundary scattering 영향을 최소화할 수 있을 것으로 보고 있다. 하지만 가혹한 electrical field와 높은 Joule heating이 발생하는 동작 환경으로 인해 performance뿐만 아니라 소자 신뢰성이 더 열악한 상황에 놓여있다. 예를 들어 차세대 금속에 대한 time dependent dielectric breakdown (TDDB) 신뢰성 문제가 보고되고 있기 때문에 이를 보안할 확산방지막 물질 및 공정연구가 필요하다. 특히 높은 전기장에서 Co ion이 유전체로 침투하여 extrinsic dielectric breakdown 신뢰성 문제가 최근 보고되고 있다. 따라서 금속 이온이 유전체 내부로 침투하는 것을 방지하여, Co 배선의 신뢰성을 향상시킬 수 견고한 확산방지막 개발 및 새로운 배선 시스템 설계가 필요한 시점이다. 또한, 배선 저항을 낮추기 위해서는 매우 얇은 확산방지막 개발이 필요하다. 신뢰성이 좋은 확산방지막이라도 배선에서 많은 영역을 차지할 경우 전체 성능이 저하되기 때문이다. Cu 확산방지막으로 사용되고 있는 TaN 층은 2.5 nm 보다 얇을 경우 신뢰성이 급격히 나빠지므로 2.5 nm보다 얇은 두께의 견고한 확산방지막 개발이 필요하다. 본 연구는 차세대 반도체 배선 물질로 주목받고 있는 Co 금속에 대하여 저저항·고신뢰성을 확보할 수 있는 Co alloy 자가형성 확산방지막 (Co alloy self-forming barrier, SFB) 소재 디자인하였다. 자가형성 확산방지막 방법론은 열처리 과정에서 금속과 유전체 계면에서 도펀트가 확산하게 된다. 그리고 확산되니 도펀트는 얇은 확산방지막을 형성하는 방법론이다. 이 방법론을 통해 금속 이온의 이동을 방지하여 Co 배선 신뢰성을 향상시킬 수 있을 것으로 예상하였다. 우선, Co 합금상에서 적절한 도펀트를 찾기 위해서 CMOS 공정에 적용 가능한 금속들을 선별하였다. 도펀트 저항, 금속간 화합물 형성 여부, Co내 고용도, Co alloy에서의 활성계수, 산화도, Co/SiO2 계면에서의 안정상을 열역학적 계산을 통해서 물질 선정 기준으로 세웠다. 열역학적 계산을 기반으로 9개의 도펀트 금속이 선택되었으며, Co 합금 자가형성 확산방지막 기준에 따라서 우선 순위를 지정하였다. 그리고 최종적으로 박막과 소자 신뢰성 평가를 통해서 가장 적합한 자가형성 확산방지막 물질을 선정하였다. X-ray photoelectron spectroscopy (XPS) 분석을 이용하여 Cr, Zn, Mn이 박막 구조의 표면으로 외부 확산 여부를 확인하고 결합 에너지 분석을 통해 외부로 확산된 도펀트의 화학적 상태를 조사하였다. 분석 결과 Cr, Zn, Mn이 유전체 계면으로 확산되어 산소와 반응하여oxide/silicate 확산 방지막 (e.g. Cr2O3, Zn2SiO4, MnSiO3)을 형성한 것을 확인하였다. 그 중 Cr은 SiO2 유전체와 함께 가장 이상적인 자기 형성 거동을 나타내며 산소와 반응하여 Cr2O3 층을 형성하는 것을 확인하였다. MIS (Metal-Insulator-Semiconductor) 구조에서도 외부로 확산된 Cr은 계면에서 SiO2와 반응하여 Cr2O3 자가형성 확산방지막이 형성되었다. 확산방지층의 두께는 약 1.2nm로 전체 유효저항을 최소화할 수 있는 충분히 얇은 두께를 확보하였다. VRDB (Voltage-Ramping Dielectric Breakdown) 테스트를 통해 Co-Cr 합금은 순수 Co보다 최대 200% 높은 항복 전압 (breakdown voltage)을 보였다. 반도체 배선 공정에 적용할 수 있는 Cr 도핑 농도와 열처리 조건의 영향을 확인하였다. Cr이 1at% 미만으로 도핑되었을 때 우수한 전기적 신뢰성을 나타내었다. 또한, 250℃ 이상에서 30분 이상 열처리를 하였을 때 Cr2O3 계면층이 형성됨을 알 수 있었다. 즉, 현재 배선 공정 온도가 400°C 미만이기 때문에 Co-Cr 합금이 배선 공정에 적용 가능함을 확인하였다. TDDB 수명 테스트도 수행되었으며 Co-Cr 합금 배선은 자체 형성된 계면층의 매우 안정적인 확산 장벽 특성을 보여주었다. DFT 분석은 Cr2O3자가형성 확산방지막이 현재 연구되고 있는 TiN 확산 장벽보다 더 높은 에너지 장벽 값을 보여주기 때문에 매우 유망한 확산방지막임을 보여주었다. 본 연구는 반도채 배선 물질 시스템에서 성능과 신뢰성을 고려한 열역학적 계산을 통해 Co 기반 자가형성 확산방지막을 설계하였다. 실험 결과 신뢰성이 우수하고 아주 얇은 Cr2O3 확산방지막이 있는 Co-Cr 합금이 제안하였다. 물질 설계와 전기적 신뢰성 검증을 Co/Cr2O3/SiO2 물질 시스템을 제안하였고 앞으로의 다가올 차세대 배선에서 구현될 수 있을 것으로 기대된다.Abstract i Table of Contents v List of Tables ix List of Figures xii Chapter 1. Introduction 1 1.1. Scaling down of VLSI systems 1 1.2. Driving force of interconnect system evolution 7 1.3. Driving force of beyond Cu interconnects 11 1.4. Objective of the thesis 18 1.5. Organization of the thesis 21 Chapter 2. Theoretical Background 22 2.1. Evolution of interconnect systems 22 2.1.1. Cu/barrier/low-k interconnect system 22 2.1.2. Process developments for interconnect reliability 27 2.1.3. 3rd generation of interconnect system 31 2.2 Thermodynamic tools for Co self-forming barrier 42 2.2.1 Binary phase diagram 42 2.2.2 Ellingham diagram 42 2.2.3 Activity coefficient 43 2.3. Reliability of Interconnects 45 2.3.1. Current conduction mechanisms in dielectrics 45 2.3.2. Reliability test vehicles 50 2.3.3. Dielectric breakdown assessment 52 2.3.4. Dielectric breakdown mechanisms 55 2.3.5. Reliability test: VRDB and TDDB 56 2.3.6. Lifetime models 57 Chapter 3. Experimental Procedures 60 3.1. Thin film deposition 60 3.1.1. Substrate preparation 60 3.1.2. Oxidation 61 3.1.3. Co alloy deposition using DC magnetron sputtering 61 3.1.4. Annealing process 65 3.2. Thin film characterization 67 3.2.1. Sheet resistance 67 3.2.2. X-ray photoelectron spectroscopy (XPS) 68 3.3. Metal-Insulator-Semiconductor (MIS) device fabrication 70 3.3.1. Patterning using lift-off process 70 3.3.2. TDDB packaging 72 3.4. Reliability analysis 74 3.4.1. Electrical reliability analysis 74 3.4.2. Transmission electron microscopy (TEM) analysis 75 3.5. Computation 76 3.5.1 FactsageTM calculation 76 3.5.2. Density Functional Theory (DFT) calculation 77 Chapter 4. Co Alloy Design for Advanced Interconnects 78 4.1. Material design of Co alloy self-forming barrier 78 4.1.1. Rule of thumb of Co-X alloy 78 4.1.2. Co alloy phase 80 4.1.3. Out-diffusion stage 81 4.1.4. Reaction step with SiO2 dielectric 89 4.1.5. Comparison criteria 94 4.2. Comparison of Co alloy candidates 97 4.2.1. Thin film resistivity evaluation 97 4.2.2. Self-forming behavior using XPS depth profile analysis 102 4.2.3. MIS device reliability test 110 4.3 Summary 115 Chapter 5. Co-Cr Alloy Interconnect with Robust Self-Forming Barrier 117 5.1. Compatibility of Co-Cr alloy SFB process 117 5.1.1. Effect of Cr doping concentration 117 5.1.2. Annealing process condition optimization 119 5.2. Reliability of Co-Cr interconnects 122 5.2.1. VRDB quality test with Co-Cr alloys 122 5.2.2. Lifetime evaluation using TDDB method 141 5.2.3. Barrier mechanism using DFT 142 5.3. Summary 145 Chapter 6. Conclusion 148 6.1. Summary of results 148 6.2. Research perspectives 150 References 151 Abstract (In Korean) 166 Curriculum Vitae 169박

MICROSTRUCTURAL IMPACT ON ELECTROMIGRATION: A TCAD STUDY

Current electromigration models used for simulation and analysis of interconnect reliability lack the appropriate description of metal microstructure and consequently have a very limited predictive capability. Therefore, the main objective of our work was obtaining more sop histicated electromigration models. The problem is addressed through a combination of different levels of atomistic modeling and already available continuum level macroscopic models. A novel method for an ab initio calculation  of the effective valence for electromigration is presented and its application on the analysis of EM behavior is demonstrated. Additionally, a simple analytical model for the early electromigration lifetime is obtained. We have shown that itsapplication gives a reasonable estimate for the early electromigration failuresincluding the effect of microstructure

Design tool and methodologies for interconnect reliability analysis in integrated circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (p. 195-204).by Syed Mohiul Alam.Ph.D

Reliability of copper interconnects in integrated circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.Includes bibliographical references.As dimensions shrink and current densities increase, the reliability of metal interconnects becomes a serious concern. In copper interconnects, the dominant diffusion path is along the interface between the copper and the top passivation layer (usually Si3N4). One of the predominant failure mechanisms in Cu has been open-circuit failure due to electromigration-induced void nucleation and growth near the cathode ends of interconnect segments. However, results from accelerated electromigration tests show that the simple failure analyses based on simple void nucleation and growth can not explain the wide range of times-to-failure that are observed, suggesting that other types of failure mechanisms are present. In this thesis, by devising and performing unique experiments through the development of an electromigration simulation tool, unexpected complex failure mechanisms have been identified that have significant effects on the reliability of copper interconnects. A simulation tool was developed by implementing the one-dimensional non-linear differential equation model first described by Korhonen et al. By applying an implicit method (Backward Euler method), the calculation time was significantly reduced, and stability increased, compared to previous tools based on explicit methods (Forward Euler method).(cont.) The tool was crosschecked with experimental results by comparing void growth rates in simulations and experiments. Using this tool, one can simulate stress and atomic concentration states over the entire length of an interconnect segment or throughout a multi-segment interconnect tree, to identify analyze possible failure locations and mechanisms. Experiments were carried out on dotted-i structures, where two 25jim-lomg segments were connected by a via in the middle. Electrical currents were applied to the two segments independently, and lifetime effects of adjacent segments were determined. Using the simulation tool and calculations, it was shown that adjacent segments have a significant effect on a segment's stress state, even if the adjacent segment has no electrical current. This explains experimental observations. This also suggests that for reliability analyses to be accurate, the states of all adjacent segments must be considered, including the ones without electrical current. In a second set of experiments, the importance of pre-existing voids was investigated. Using in-situ scanning electron microscopy, voids away from the cathode were observed. These voids grew and drifted toward the cathode and the shape of the voids were found to be closely related to the texture and stress state of individual grains in the interconnect.(cont.) The drift velocity of voids was shown to be directly proportional to surface diffusivity. Electromigration tests on unpassivated samples were performed under vacuum to obtain the surface diffusivity of copper and its dependence on texture orientations. Simulation results show that pre-existing voids cause void growth away from the cathode. Subsequent failure mechanisms differ depending on the location of the pre-existing void and the critical void volume for de-pinning from grain boundaries. If pre-existing voids are present, void-growth-limited failure is expected in interconnects at low current densities, due to growth of pre-existing void, and the lifetimes are expected to scale inversely with j. However, at higher current densities (typical for accelerated testing), failure can occur through nucleation of new voids at the cathode (so that lifetimes scale inversely with j2), or through a mixture of nucleation of new voids and growth of pre-existing voids. These effects must be taken into account to accurately project the reliability of interconnects under service conditions, based on experiments carried out under accelerated conditions.by Zung-Sun Choi.Ph.D

Thermal profiling in CMOS/memristor hybrid architectures

CMOS/memristor hybrid architectures combine conventional CMOS processing elements with thin-film memristor-based crossbar circuits for high-density reconfigurable systems. These architectures have received an explosive growth in research over the past few years due to the first practical demonstration of a thin-film memristor in 2008. The reliability and lifetimes of both the CMOS and memristor partitions of these architectures are severely affected by temperature variations across the chip. Therefore, it is expected that dynamic thermal management (DTM) mechanisms will be needed to improve their reliability and lifetime. This thesis explores one aspect of DTM--thermal profiling--in a CMOS/memristor memory architecture. A temperature sensing resistive random access memory (TSRRAM) was designed. Temperature information is extracted from the TSRRAM by measuring the write time of thin-film memristors. Active and passive sensing mechanisms are also introduced as means for DTM algorithms to determine the thermal profile of the chip. Crosstherm, a simulation framework, was developed to analyze the effects of temperature variations in CMOS/memristor architectures. The TSRRAM design was simulated using the Crosstherm framework for four CMOS processor benchmarks. Passive sensing produced a mean absolute sensor error across all benchmarks of 2.14 K. The size of the DTM unit\u27s memory was also shown to have a significant impact on the accuracy of extracted thermal data during passive sensing. Active sensing was also demonstrated to show the effect of dynamic adjustment of sensor resolution on the accuracy of hotspot temperature estimations