Principles of Neuromorphic Photonics

In an age overrun with information, the ability to process reams of data has become crucial. The demand for data will continue to grow as smart gadgets multiply and become increasingly integrated into our daily lives. Next-generation industries in artificial intelligence services and high-performance computing are so far supported by microelectronic platforms. These data-intensive enterprises rely on continual improvements in hardware. Their prospects are running up against a stark reality: conventional one-size-fits-all solutions offered by digital electronics can no longer satisfy this need, as Moore's law (exponential hardware scaling), interconnection density, and the von Neumann architecture reach their limits. With its superior speed and reconfigurability, analog photonics can provide some relief to these problems; however, complex applications of analog photonics have remained largely unexplored due to the absence of a robust photonic integration industry. Recently, the landscape for commercially-manufacturable photonic chips has been changing rapidly and now promises to achieve economies of scale previously enjoyed solely by microelectronics. The scientific community has set out to build bridges between the domains of photonic device physics and neural networks, giving rise to the field of \emph{neuromorphic photonics}. This article reviews the recent progress in integrated neuromorphic photonics. We provide an overview of neuromorphic computing, discuss the associated technology (microelectronic and photonic) platforms and compare their metric performance. We discuss photonic neural network approaches and challenges for integrated neuromorphic photonic processors while providing an in-depth description of photonic neurons and a candidate interconnection architecture. We conclude with a future outlook of neuro-inspired photonic processing.Comment: 28 pages, 19 figure

로직 및 피지컬 합성에서의 타이밍 분석과 최적화

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 김태환.Timing analysis is one of the necessary steps in the development of a semiconductor circuit. In addition, it is increasingly important in the advanced process technologies due to various factors, including the increase of process–voltage–temperature variation. This dissertation addresses three problems related to timing analysis and optimization in logic and physical synthesis. Firstly, most static timing analysis today are based on conventional fixed flip-flop timing models, in which every flip-flop is assumed to have a fixed clock-to-Q delay. However, setup and hold skews affect the clock-to-Q delay in reality. In this dissertation, I propose a mathematical formulation to solve the problem and apply it to the clock skew scheduling problems as well as to the analysis of a given circuit, with a scalable speedup technique. Secondly, near-threshold computing is one of the promising concepts for energy-efficient operation of VLSI systems, but wide performance variation and nonlinearity to process variations block the proliferation. To cope with this, I propose a holistic hardware performance monitoring methodology for accurate timing prediction in a near-threshold voltage regime and advanced process technology. Lastly, an asynchronous circuit is one of the alternatives to the conventional synchronous style, and asynchronous pipeline circuit especially attractive because of its small design effort. This dissertation addresses the synthesis problem of lightening two-phase bundled-data asynchronous pipeline controllers, in which delay buffers are essential for guaranteeing the correct handshaking operation but incurs considerable area increase.타이밍 분석은 반도체 회로 개발 필수 과정 중 하나로, 최신 공정일수록 공정-전압-온도 변이 증가를 포함한 다양한 요인으로 하여금 그 중요성이 커지고 있다. 본 논문에서는 로직 및 피지컬 합성과 관련하여 세 가지 타이밍 분석 및 최적화 문제에 대해 다룬다. 첫째로, 오늘날 대부분의 정적 타이밍 분석은 모든 플립-플롭의 클럭-출력 딜레이가 고정된 값이라는 가정을 바탕으로 이루어졌다. 하지만 실제 클럭-출력 딜레이는 해당 플립-플롭의 셋업 및 홀드 스큐에 영향을 받는다. 본 논문에서는 이러한 특성을 수학적으로 정리하였으며, 이를 확장 가능한 속도 향상 기법과 더불어 주어진 회로의 타이밍 분석 및 클럭 스큐 스케쥴링 문제에 적용하였다. 둘째로, 유사 문턱 연산은 초고집적 회로 동작의 에너지 효율을 끌어 올릴 수 있다는 점에서 각광받지만, 큰 폭의 성능 변이 및 비선형성 때문에 널리 활용되고 있지 않다. 이를 해결하기 위해 유사 문턱 전압 영역 및 최신 공정 노드에서 보다 정확한 타이밍 예측을 위한 하드웨어 성능 모니터링 방법론 전반을 제안하였다. 마지막으로, 비동기 회로는 기존 동기 회로의 대안 중 하나로, 그 중에서도 비동기 파이프라인 회로는 비교적 적은 설계 노력만으로도 구현 가능하다는 장점이 있다. 본 논문에서는 2위상 묶음 데이터 프로토콜 기반 비동기 파이프라인 컨트롤러 상에서, 정확한 핸드셰이킹 통신을 위해 삽입된 딜레이 버퍼에 의한 면적 증가를 완화할 수 있는 합성 기법을 제시하였다.1 INTRODUCTION 1 1.1 Flexible Flip-Flop Timing Model 1 1.2 Hardware Performance Monitoring Methodology 4 1.3 Asynchronous Pipeline Controller 10 1.4 Contributions of this Dissertation 15 2 ANALYSIS AND OPTIMIZATION CONSIDERING FLEXIBLE FLIP-FLOP TIMING MODEL 17 2.1 Preliminaries 17 2.1.1 Terminologies 17 2.1.2 Timing Analysis 20 2.1.3 Clock-to-Q Delay Surface Modeling 21 2.2 Clock-to-Q Delay Interval Analysis 22 2.2.1 Derivation 23 2.2.2 Additional Constraints 26 2.2.3 Analysis: Finding Minimum Clock Period 28 2.2.4 Optimization: Clock Skew Scheduling 30 2.2.5 Scalable Speedup Technique 33 2.3 Experimental Results 37 2.3.1 Application to Minimum Clock Period Finding 37 2.3.2 Application to Clock Skew Scheduling 39 2.3.3 Efficacy of Scalable Speedup Technique 43 2.4 Summary 44 3 HARDWARE PERFORMANCE MONITORING METHODOLOGY AT NTC AND ADVANCED TECHNOLOGY NODE 45 3.1 Overall Flow of Proposed HPM Methodology 45 3.2 Prerequisites to HPM Methodology 47 3.2.1 BEOL Process Variation Modeling 47 3.2.2 Surrogate Model Preparation 49 3.3 HPM Methodology: Design Phase 52 3.3.1 HPM2PV Model Construction 52 3.3.2 Optimization of Monitoring Circuits Configuration 54 3.3.3 PV2CPT Model Construction 58 3.4 HPM Methodology: Post-Silicon Phase 60 3.4.1 Transfer Learning in Silicon Characterization Step 60 3.4.2 Procedures in Volume Production Phase 61 3.5 Experimental Results 62 3.5.1 Experimental Setup 62 3.5.2 Exploration of Monitoring Circuits Configuration 64 3.5.3 Effectiveness of Monitoring Circuits Optimization 66 3.5.4 Considering BEOL PVs and Uncertainty Learning 68 3.5.5 Comparison among Different Prediction Flows 69 3.5.6 Effectiveness of Prediction Model Calibration 71 3.6 Summary 73 4 LIGHTENING ASYNCHRONOUS PIPELINE CONTROLLER 75 4.1 Preliminaries and State-of-the-Art Work 75 4.1.1 Bundled-data vs. Dual-rail Asynchronous Circuits 75 4.1.2 Two-phase vs. Four-phase Bundled-data Protocol 76 4.1.3 Conventional State-of-the-Art Pipeline Controller Template 77 4.2 Delay Path Sharing for Lightening Pipeline Controller Template 78 4.2.1 Synthesizing Sharable Delay Paths 78 4.2.2 Validating Logical Correctness for Sharable Delay Paths 80 4.2.3 Reformulating Timing Constraints of Controller Template 81 4.2.4 Minimally Allocating Delay Buffers 87 4.3 In-depth Pipeline Controller Template Synthesis with Delay Path Reusing 88 4.3.1 Synthesizing Delay Path Units 88 4.3.2 Validating Logical Correctness of Delay Path Units 89 4.3.3 Updating Timing Constraints for Delay Path Units 91 4.3.4 In-depth Synthesis Flow Utilizing Delay Path Units 95 4.4 Experimental Results 99 4.4.1 Environment Setup 99 4.4.2 Piecewise Linear Modeling of Delay Path Unit Area 99 4.4.3 Comparison of Power, Performance, and Area 102 4.5 Summary 107 5 CONCLUSION 109 5.1 Chapter 2 109 5.2 Chapter 3 110 5.3 Chapter 4 110 Abstract (In Korean) 127Docto

CMOS array design automation techniques

A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Reliability Prediction with MTOL

Here, we develop a comprehensive reliability prediction of FPGA devices solely from data motivated by physics of failure. The Multiple Temperature Operational Life (MTOL) testing method calculates the failure in time (FIT) of 3 different failure mechanisms on both 45nm and 28nm technologies. From a comparison of the two technologies, we found significant hot carrier injection (HCI) and Electromigration (EM) throughout the operating range in 45nm technology. However, it seems that 28nm exhibits no HCI or EM degradation even up to 1.6V on the core. As a result, we show that there is no effect of frequency on the reliability for that technology. This means that at 28nm, the devices can be de-rated or up-rated based only on the NBTI model and therefore reliability is dependent only on operating Voltage and Temperature with a single activation energy. Notably, the activation energies and voltage acceleration factors for both technologies are remarkably similar. This demonstration shows that, unlike other conventional qualification procedures, the MTOL testing procedure gives a broad description of the reliability in sub-zero and high temperatures. This procedure provides FIT prediction using reduced materials and test time, which can be applied to newer technologies, specifically 20nm and 16nm and beyond

Additively Manufactured RF Components, Packaging, Modules, and Flexible Modular Phased Arrays Enabling Widespread Massively Scalable mmWave/5G Applications

The 5G era is here and with it comes many challenges, particularily facing the high frequency mmWave adoption. This is because of the cost to implement such dense networks is much greater due to the high propagation losses of signals that range from 26 GHz to 40 GHz. Therefore there needs to be a way to utilize a method of fabrication that can change with the various environments that 5G will be deployed in, be it dense urban areas or suburban sprawl. In this research, the focus is on making these RF components utilized for 5G at low cost and modular with a focus on additive manufacturing. Since additive manufacturing is a rapid prototyping technique, the technology can be quickly adjusted and altered to meet certain specifications with negligible overhead. Several areas of research will be explored. Firstly, various RF passive components such as additively manufactured antennas and couplers with a combination hybrid inkjet and 3D printing will be discussed. Passive components are critical for evaluating the process of additive manufacturing for high frequency operation. Secondly, various structures will be evaluated specifically for packaging mmWave ICs, including interconnects, smart packaging and encapsulants for use in single or multichip modules. Thirdly, various antenna fabrication techniques will be explored which enables fully integrated ICs with antennas, called System on Antenna (SoA) which utilizes both inkjet and 3D printing to combine antennas and ICs into modules. These modules, can then be built into arrays in a modular fashion, allowing for large or smaller arrays to be assembled on the fly. Finally, a method of calibrating the arrays is introduced, utilizing inkjet printed sensors. This allows the sensor to actively detect bends and deformations in the array and restore optimal antenna array performance. Built for flexible phased arrays, the sensor is designed for implementation for ubiquitous use, meaning that its can be placed on any surface, which enables widespread use of 5G technologies.Ph.D

Application of effective medium theory to the analysis of integrated circuit interconnects

The design and physical verification of contemporary integrated circuits is a challenging task due to their complexity. System-in-Package is an example of generally congested electronic components and interconnects which in the initial design process rely on computationally intensive electromagnetic simulations. Hence the available computer memory capacity and computational speed become meaningful limitations. An alternative method which allows the designer to overcome or reduce the limits is desired. This work represents the first demonstration of the application of effective medium theory to the analysis of those segments of the entire integrated system where the interconnect networks are more dense. The presented approach takes advantage of the deep subwavelength characteristic of interconnect structures. In order to achieve the aim of defining the homogeneous equivalent for the interconnect grating structure a few steps were followed towards proving the homogenisation concept and finally presenting it by an analytical formulation. A set of parameters (metal fill factor, aspect ratio, dielectric background and period-to-wavelength ratio) with values related to typical design rules were considered. Relating these parameters allows the empirical models to be defined. In order to show the relationship between existing effective medium theories and those developed in this Thesis, the presented empirical models are defined in terms of the Maxwell-Garnett mixing rule with an additional scaling factor. The distribution of the scaling factor was analysed in terms of the calculated reflection and transmission coefficients of the homogenised structures that are equivalent to a given grating geometry. Finally the scaling factor, for each empirical model, was expressed by an analytical formula and the models validated by their application to the numerical analysis of grating structures. The numerical validation was carried out by comparing the reflection and transmission coefficients obtained for the detailed and homogenised structures. In order to ensure the empirical models can be broadly employed, the performance of the model in the presence of non-normally incident plane wave was evaluated. For the range of angles ±30º the model is accurate to 5%. The impact of the shape of the grating, specifically the case of a tapered profile, typical of actual fabricated interconnects was also considered, with sidewall tapers of up to 5º giving the same error not higher than 5%. Experimental validation of the application of the homogenisation concept to the analysis of interconnects is desired for two main applications: for the reflectivity estimation of a whole chip in a System-in-Package and for the performance estimation of interconnects on lower metal layers in an interconnect stack. For the first, free-space measurements are taken of a grating plate with copper rods aligned in parallel illuminated by a plane wave in the X-band (8.2-12.4 GHz). For the second, S-parameters are measured for microstrip waveguides with a number of metal rods embedded in the substrate between the signal line and ground plane. The good agreement with the simulations validates the homogenisation approach for the analysis of interconnects