Process and Temperature Compensated Wideband Injection Locked Frequency Dividers and their Application to Low-Power 2.4-GHz Frequency Synthesizers

There has been a dramatic increase in wireless awareness among the user community in the past five years. The 2.4-GHz Industrial, Scientific and Medical (ISM) band is being used for a diverse range of applications due to the following reasons. It is the only unlicensed band approved worldwide and it offers more bandwidth and supports higher data rates compared to the 915-MHz ISM band. The power consumption of devices utilizing the 2.4-GHz band is much lower compared to the 5.2-GHz ISM band. Protocols like Bluetooth and Zigbee that utilize the 2.4-GHz ISM band are becoming extremely popular. Bluetooth is an economic wireless solution for short range connectivity between PC, cell phones, PDAs, Laptops etc. The Zigbee protocol is a wireless technology that was developed as an open global standard to address the unique needs of low-cost, lowpower, wireless sensor networks. Wireless sensor networks are becoming ubiquitous, especially after the recent terrorist activities. Sensors are employed in strategic locations for real-time environmental monitoring, where they collect and transmit data frequently to a nearby terminal. The devices operating in this band are usually compact and battery powered. To enhance battery life and avoid the cumbersome task of battery replacement, the devices used should consume extremely low power. Also, to meet the growing demands cost and sized has to be kept low which mandates fully monolithic implementation using low cost process. CMOS process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. A fully integrated solution is attractive for low power consumption as it avoids the need for power hungry drivers for driving off-chip components. The transceiver is often the most power hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator in the transmitter’s frequency synthesizer are among the major sources of power consumption. There have been a number of publications in the past few decades on low-power high-performance VCOs. Therefore this work focuses on prescalers. A class of analog frequency dividers called as Injection-Locked Frequency Dividers (ILFD) was introduced in the recent past as low power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However the range of operation frequency also knows as the locking range is limited. ILFDs can be classified as LC based and Ring based. Though LC based are insensitive to process and temperature variation, they cannot be used for the 2.4-GHz ISM band because of the large size of on-chip inductors at these frequencies. This causes a lot of valuable chip area to be wasted. Ring based ILFDs are compact and provide a low power solution but are extremely sensitive to process and temperature variations. Process and temperature variation can cause ring based ILFD to loose lock in the desired operating band. The goal of this work is to make the ring based ILFDs useful for practical applications. Techniques to extend the locking range of the ILFDs are discussed. A novel and simple compensation technique is devised to compensate the ILFD and keep the locking range tight with process and temperature variations. The proposed ILFD is used in a 2.4-GHz frequency synthesizer that is optimized for fractional-N synthesis. Measurement results supporting the theory are provided

Low jitter phase-locked loop clock synthesis with wide locking range

The fast growing demand of wireless and high speed data communications has driven efforts to increase the levels of integration in many communications applications. Phase noise and timing jitter are important design considerations for these communications applications. The desire for highly complex levels of integration using low cost CMOS technologies works against the minimization of timing jitter and phase noise for communications systems which employ a phase-locked loop for frequency and clock synthesis with on-chip VCO. This dictates an integrated CMOS implementation of the VCO with very low phase noise performance. The ring oscillator VCOs based on differential delay cell chains have been used successfully in communications applications, but thermal noise induced phase noise have to be minimized in order not to limit their applicability to some applications which impose stringent timing jitter and phase noise requirements on the PLL clock synthesizer. Obtaining lower timing jitter and phase noise at the PLL output also requires the minimization of noise in critical circuit design blocks as well as the optimization of the loop bandwidth of the PLL. In this dissertation the fundamental performance limits of CMOS PLL clock synthesizers based on ring oscillator VCOs are investigated. The effect of flicker and thermal noise in MOS transistors on timing jitter and phase noise are explored, with particular emphasis on source coupled NMOS differential delay cells with symmetric load elements. Several new circuit architectures are employed for the charge pump circuit and phase-frequency detector (PFD) to minimize the timing jitter due to the finite dead zone in the PFD and the current mismatch in the charge pump circuit. The selection of the optimum PLL loop bandwidth is critical in determining the phase noise performance at the PLL output. The optimum loop bandwidth and the phase noise performance of the PLL is determined using behavioral simulations. These results are compared with transistor level simulated results and experimental results for the PLL clock synthesizer fabricated in a 0.35 µm CMOS technology with good agreement. To demonstrate the proposed concept, a fully integrated CMOS PLL clock synthesizer utilizing integer-N frequency multiplier technique to synthesize several clock signals in the range of 20-400 MHz with low phase noise was designed. Implemented in a standard 0.35-µm N-well CMOS process technology, the PLL achieves a period jitter of 6.5-ps (rms) and 38-ps (peak-to-peak) at 216 MHz with a phase noise of -120 dBc/Hz at frequency offsets above 10 KHz. The specific research contributions of this work include (1) proposing, designing, and implementing a new charge pump circuit architecture that matches current levels and therefore minimizes one source of phase noise due to fluctuations in the control voltage of the VCO, (2) an improved phase-frequency detector architecture which has improved characteristics in lock condition, (3) an improved ring oscillator VCO with excellent thermal noise induced phase noise characteristics, (4) the application of selfbiased techniques together with fixed bias to CMOS low phase noise PLL clock synthesizer for digital video communications ,and (5) an analytical model that describes the phase noise performance of the proposed VCO and PLL clock synthesizer

FULLY INTEGRATED HIGH-FREQUENCY CLOCK GENERATION AND SYNCHRONIZATION TECHINIQUES

Department of Electrical EngineeringThis thesis presents clock generation and synchronization techniques for RF wireless communication. First, it deals with voltage-controlled oscillators (VCOs) for local oscillators (LO) in transceivers, and secondly delay-locked loops for synchronization. For the high-performance LO, VCO is one of the key blocks. LC VCOs and ring VCOs are commonly-used types. Their characteristics are varied for different frequency bands. In this thesis, two types of VCOs, LC VCO and ring VCO, are presented with specific applications. For the multi-clock generator which could be used for carrier aggregation or frequency hopping, ring-type digitally controlled oscillator (DCO) was designed covering 900-1200 MHz with -165 dB FOM. For the multi-band frequency synthesizer which could be used for 5G communication with backward compatibility, three LC VCOs are designed which frequency range of 25-30 GHz for 5G, 5.2-6.0 GHz for LTE, 2.7-4.2 GHz for 2G-3G communication, respectively. For the clock synchronization in RF communications, a delay-locked loop (DLL) using a digital-to-analog converter (DAC) based band-selecting circuit (BSC) was presented to achieve a wide harmonic-locking-free frequency range. The BSC used the proposed exponential digital-to-analog converter (EDAC) to generate a collection of initial control voltages which follow a sequence of geometric with satisfying the condition for preventing harmonic locking problem. Therefore, the BSC can cover a much wider frequency range which is free from harmonic locking problem compared to initial band selection techniques using conventional, linear DAC (LDAC) that have a set of control voltages of arithmetic sequence. In this thesis, the DLL was implemented in a 65-nm CMOS process, and it had a measured frequency range from 100 to 1500 MHz which range is free from harmonic locking. The measure rms jitter and 1-MHz phase noise at 1000 MHz were 1.99 ps and ?28 dBc/Hz, respectively. The DLL consumes 5.5 mW and its active area was 0.052 mm2.clos

LOW-JITTER AND LOW-SPUR RING-OSCILLATOR-BASED PHASE-LOCKED LOOPS

Department of Electrical EngineeringIn recent years, ring-oscillator based clock generators have drawn a lot of attention due to the merits of high area efficiency, potentially wide tuning range, and multi-phase generation. However, the key challenge is how to suppress the poor jitter of ring oscillators. There have been many efforts to develop a ring-oscillator-based clock generator targeting very low-jitter performance. However, it remains difficult for conventional architectures to achieve both low RMS jitter and low levels of reference spurs concurrently while having a high multiplication factor. In this dissertation, a time-domain analysis is presented that provides an intuitive understanding of RMS jitter calculation of the clock generators from their phase-error correction mechanisms. Based on this analysis, we propose new designs of a ring-oscillator-based PLL that addresses the challenges of prior-art ring-based architectures. This dissertation introduces a ring-oscillator-based PLL with the proposed fast phase-error correction (FPEC) technique, which emulates the phase-realignment mechanism of an injection-locked clock multiplier (ILCM). With the FPEC technique, the phase error of the voltage-controlled oscillator (VCO) is quickly removed, achieving ultra-low jitter. In addition, in the transfer function of the proposed architecture, an intrinsic integrator is involved since it is naturally based on a PLL topology. The proposed PLL can thus have low levels of reference spurs while maintaining high stability even for a large multiplication factor. Furthermore, it presents another design of a digital PLL embodying the FPEC technique (or FPEC DPLL). To overcome the problem of a conventional TDC, a low-power optimally-spaced (OS) TDC capable of effectively minimizing the quantization error is presented. In the proposed FPEC DPLL, background digital controllers continuously calibrate the decision thresholds and the gain of the error correction by the loop to be optimal, thus dramatically reducing the quantization error. Since the proposed architecture is implemented in a digital fashion, the variables defining the characteristics of the loop can be easily estimated and calibrated by digital calibrators. As a result, the performances of an ultra-low jitter and the figure-of-merit can be achieved.clos

Fast Digital Calibration of Static Phase Offset in Charge-Pump Phase-Locked Loops

Mismatches within the charge pump (CP) deteriorate the spectral perfor- mance of the CP-PLL output signal resulting in a static phase offset. Classical analog approaches to reducing this offset consume large silicon area and increase gate leak- age mismatch. For ultra-deep-submicron (UDSM) technologies where gate leakage in- creases dramatically, reduction of static phase offset through digital calibration becomes more favorable. This paper presents a novel technique which digitally calibrates static phase offset down to < 10 ps for a PLL operating at 4.8 GHz, designed using a 1V 90nm CMOS process. Calibration is completed in only 2 steps, making the proposed technique suitable for systems requiring frequent switching such as frequency hopping systems commonly used in today’s wireless communication systems

Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications

High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.052 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator

Switched Capacitor Loop Filter 와 Source Switched Charge Pump 를 이용한 Phase-Locked Loop 의 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.This thesis proposes a low integrated RMS jitter and low reference spur phase locked loop (PLL) using a switched capacitor loop filter and source switched charge pump. The PLL employs a single tunable charge pump which reduces current mis match across wide control voltage range and charge sharing effect to get high perfor mance of reference spur level. The switched capacitor loop filter is adopted to achieve insensitivity to temperature, supply voltage, and process variation of a resistor. The proposed PLL covers a wide frequency range and has a low integrated RMS jitter and low reference spur level to target various interface standards. The mechanism of switched capacitor loop filter and source switched charge pump is analyzed. Fabricated in 40 nm CMOS technology, the proposed analog PLL provides four phase for a quarter-rate transmitter, consumes 6.35 mW at 12 GHz using 750 MHz reference clock, and occupies an 0.008 mm2 with an integrated RMS jitter (10 kHz to 100 MHz) of 244.8 fs. As a result, the PLL achieves a figure of merit (FoM) of -244.2 dB with high power efficiency of 0.53 mW/GHz, and reference spur level is -60.3 dBc.본 논문에서는 낮은 RMS jitter 와 낮은 레퍼런스 스퍼를 가지며 스위치축전기 루프 필터와 소스 스위치 전하 펌프를 이용한 PLL 을 제안한다. 제안된 PLL 은 레퍼런스 스퍼의 성능을 위해 넓은 컨트롤 전압의 범위 동안 전류의 오차를 줄여주고 전하 공유 효과를 줄여주는 하나의 조절 가능한 전하 펌프를 사용하였다. 저항의 온도, 공급 전압, 공정 변화에 따른 민감도를 낮추기 위해 스위치 축전기 루프 필터가 사용되었다. 다양한 인터페이스 표준을 지원하기 위해 제안하는 PLL 은 넓은 주파수 범위를 지원하고 낮은 RMS jitter 와 낮은 레퍼런스 스퍼를 갖는다. 스위치 축전기 루프 필터와 소스 스위치 전하 펌프의 동작 원리에 대해 분석하였다. 40 nm CMOS 공정으로 제작되었으며, 제안된 회로는 quarter-rate 송신기를 위해 4 개의 phase 를 만들어내며 750 MHz 의 레퍼런스 클락을 이용하여 12 GHz 에서 6.35 mW 의 power 를 소모하고 0.008mm2 의 유효 면적을 차지하고 10 kHz 부터 100 MHz 까지 적분했을 때의 RMS jitter 값은 244.8fs 이다. 제안하는 PLL 은 -244.2 dB 의 FoM, 0.53 mW/GHz 의 power 효율을 달성했으며 레퍼런스 스퍼는 -60.3 dBc 이다CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUNDS 4 2.1 CLOCK GENERATION IN SERIAL LINK 4 2.2 PLL BUILDING BLOCKS 6 2.2.1 OVERVIEW 6 2.2.2 PHASE FREQUENCY DETECTOR 7 2.2.3 CHARGE PUMP AND LOOP FILTER 9 2.2.4 VOLTAGE CONTROLLED OSCILLATOR 10 2.2.5 FREQUENCY DIVIDER 13 2.3 PLL LOOP ANALYSIS 15 CHAPTER 3 PLL WITH SWITCHED CAPACITOR LOOP FILTER AND SOURCE SWITCHED CHARGE PUMP 19 3.1 DESIGN CONSIDERATION 19 3.2 PROPOSED ARCHITECTURE 21 3.3 CIRCUIT IMPLEMENTATION 23 3.3.1 PHASE FREQUENCY DETECTOR 23 3.3.2 SOURCE SWITCHED CHARGE PUMP 26 3.3.3 SWITCHED CAPACITOR LOOP FILTER 30 3.3.4 VOLTAGE CONTROLLED OSCILLATOR 35 3.3.5 POST VCO AMPLIFIER 39 3.3.6 FREQUENCY DIVIDER 40 CHAPTER 4 MEASUREMENT RESULTS 43 4.1 CHIP PHOTOMICROGRAPH 43 4.2 MEASUREMENT SETUP 45 4.3 MEASURED PHASE NOISE AND REFERENCE SPUR 47 4.4 PERFORMANCE SUMMARY 50 CHAPTER 5 CONCLUSION 52 BIBLIOGRAPHY 53 초 록 58석

Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and +-35ps Jitter

A fully integrated phase-locked loop (PLL) fabricated in a 0.24 micrometer, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24 micrometer CMOS technology. Also it has very low peak-to-peak jitter less than +-35ps at 1.25GHz output frequency

Low jitter design techniques for monolithic CMOS phase-locked and delay-locked systems

Timing jitter is a major concern in almost every type of communication system. Yet the desire for high levels of integration works against minimization of this error, especially for systems employing a phase-locked loop (PLL) or delay-locked loop (DLL) for timing generation or timing recovery. There has been an increasing demand for fully-monolithic CMOS PLL and DLL designs with good jitter performance. In this thesis, the system level as well as the transistor level low jitter design techniques for integrated PLLs and DLLs have been explored.;On the system level, a rigorous jitter analysis method based on a z-domain model is developed, in which the jitter is treated as a random event. Combined with statistical methods, the rms value of the accumulated jitter can be expressed with a closed form solution that successfully ties the jitter performance with loop parameters. Based on this analysis, a cascaded PLL/DLL structure is proposed which combines the advantage of both loops. The resulting system is able to perform frequency synthesis with the jitter as low as that of a DLL.;As an efficient tool to predict the jitter performance of a PLL or DLL system, a new nonlinear behavioral simulator is developed based on a novel behavioral modeling of the VCO and delay-line. Compared with prior art, this simulator not only simplifies the computation but also enables the noise simulation. Both jitter performance during tracking and lock condition can be predicted. This is also the first reported top-level simulation tool for DLL noise simulation.;On the transistor level, three prototype chips for different applications were implemented and tested. The first two chips are the application of PLL in Gigabit fibre channel transceivers. High speed circuit blocks that have good noise immunity are the major design concern. Testing results show that both designs have met the specifications with low power dissipation. For the third chip, an adaptive on-chip dynamic skew calibration technique is proposed to realize a precise delay multi-phase clock generator, which is a topic that has not been addressed in previous work thus far. Experimental results strongly support the effectiveness of the calibration scheme. At the same time, this design achieves by far the best reported jitter performance

A 14-channel 7 GHz VCO-based EPR-on-a-chip sensor with rapid scan capabilities

This paper presents a VCO-based EPR-on-a-chip (EPRoC) sensor for portable, battery-operated electron paramagnetic resonance (EPR) spectrometers. The proposed chip contains an array of 14 injection-locked VCOs as the sensing element for an improved sensitive volume and phase noise performance. By cointegrating a high-bandwidth PLL, the presented design allows for continuous-wave and rapid-scan EPR experiments with a minimum number of external components. The active loop filter introduces an assisted replica charge pump that mitigates the slewing requirements on the loop-filter amplifier. The measured spin sensitivity of 2×10 9 spins/Hz−−−√ together with the large active volume of 210 nl lead to an 8-fold improvement in concentration sensitivity compared to the state-of-the-art in EPRoC detectors