Mismatches within the charge pump (CP) deteriorate the spectral perfor-
mance of the CP-PLL output signal resulting in a static phase offset. Classical analog
approaches to reducing this offset consume large silicon area and increase gate leak-
age mismatch. For ultra-deep-submicron (UDSM) technologies where gate leakage in-
creases dramatically, reduction of static phase offset through digital calibration becomes
more favorable. This paper presents a novel technique which digitally calibrates static
phase offset down to < 10 ps for a PLL operating at 4.8 GHz, designed using a 1V
90nm CMOS process. Calibration is completed in only 2 steps, making the proposed
technique suitable for systems requiring frequent switching such as frequency hopping
systems commonly used in today’s wireless communication systems
