AC^0[p] Lower Bounds Against MCSP via the Coin Problem

Minimum Circuit Size Problem (MCSP) asks to decide if a given truth table of an n-variate boolean function has circuit complexity less than a given parameter s. We prove that MCSP is hard for constant-depth circuits with mod p gates, for any prime p >= 2 (the circuit class AC^0[p]). Namely, we show that MCSP requires d-depth AC^0[p] circuits of size at least exp(N^{0.49/d}), where N=2^n is the size of an input truth table of an n-variate boolean function. Our circuit lower bound proof shows that MCSP can solve the coin problem: distinguish uniformly random N-bit strings from those generated using independent samples from a biased random coin which is 1 with probability 1/2+N^{-0.49}, and 0 otherwise. Solving the coin problem with such parameters is known to require exponentially large AC^0[p] circuits. Moreover, this also implies that MAJORITY is computable by a non-uniform AC^0 circuit of polynomial size that also has MCSP-oracle gates. The latter has a few other consequences for the complexity of MCSP, e.g., we get that any boolean function in NC^1 (i.e., computable by a polynomial-size formula) can also be computed by a non-uniform polynomial-size AC^0 circuit with MCSP-oracle gates

Complexity of Nondeterministic Functions

The complexity of a nondeterministic function is the minimum possible complexity of its determinisation. The entropy of a nondeterministic function, F, is minus the logarithm of the ratio between the number of determinisations of F and the number of all deterministic functions. We obtain an upper bound on the complexity of a nondeterministic function with restricted entropy for the worst case. These bounds have strong applications in the problem of algorithm derandomization. A lot of randomized algorithms can be converted to deterministic ones if we have an effective hitting set with certain parameters (a set is hitting for a set system if it has a nonempty intersection with any set from the system). Linial, Luby, Saks and Zuckerman (1993) constructed the best effective hitting set for the system of k-value, n-dimensional rectangles. The set size is polynomial in k log n / epsilon. Our bounds of nondeterministic functions complexity offer a possibility to construct an effective hitting set for this system with almost linear size in k log n / epsilon

Formal Power Analysis of Systems-on-Chip

The design methods and languages targeted to modern System-on-Chip designs are facing tremendous pressure of the ever-increasing complexity, power, and speed requirements. To estimate any of these three metrics, there is a trade-off between accuracy and abstraction level of detail in which a system under design is analyzed. The more detailed the description, the more accurate the simulation will be, but, on the other hand, the more time consuming it will be. Moreover, a designer wants to make decisions as early as possible in the design flow to avoid costly design backtracking. To answer the challenges posed upon System-on-chip designs, this thesis introduces a formal, power aware framework, its development methods, and methods to constraint and analyze power consumption of the system under design. This thesis discusses on power analysis of synchronous and asynchronous systems not forgetting the communication aspects of these systems. The presented framework is built upon the Timed Action System formalism, which offer an environment to analyze and constraint the functional and temporal behavior of the system at high abstraction level. Furthermore, due to the complexity of System-on-Chip designs, the possibility to abstract unnecessary implementation details at higher abstraction levels is an essential part of the introduced design framework. With the encapsulation and abstraction techniques incorporated with the procedure based communication allows a designer to use the presented power aware framework in modeling these large scale systems. The introduced techniques also enable one to subdivide the development of communication and computation into own tasks. This property is taken into account in the power analysis part as well. Furthermore, the presented framework is developed in a way that it can be used throughout the design project. In other words, a designer is able to model and analyze systems from an abstract specification down to an implementable specification.Siirretty Doriast

Design and Silicon Area Optimization of Time-Domain GNSS Receiver Baseband Architectures

The use of Global Navigation Satellite Systems (GNSSs) in a wide range of portable devices has exploded in the recent years. Demands for a lower cost while expecting longer battery life and better performance are constantly increasing. The general GNSS receiver operation and algorithms are already well studied in the literature, but the hardware architectures and designs have not been discussed in detail.This thesis introduces a high level gate count estimation method that provides good accuracy without requiring the hardware being fully specified. It is based on developing hierarchical models, which are parameterizable, while requiring minimal amount of information about the silicon technology used for the implementation. The average accuracy has been shown to be 4%.Three time-domain, real-time GNSS receiver baseband architectures are described with a discussion about various optimization methods for efficient implementation: the correlator, the matched filter, and the group correlator, which is a new architecture combining some of the features of the two first ones.Four use cases are defined for different GNSS operating modes: Acquisition, tracking, assisted GNSS, and the combination of the first three modes. A comparison is made for receiver basebands including all necessary blocks for full functionality to find out which of the three architectures provides the most silicon area efficient implementation.It is shown that the correlator offers good flexibility, but yields the highest silicon area for acquisition use cases. The matched filter is best suited for the acquisition, but has large overhead when it comes to tracking the signals. The group correlator offers a reasonably good flexibility and area efficiency in all use cases.The main contributions of the thesis are: Development of domain specific optimizations for GNSS receivers and an accurate gate count estimation method, which are applied for a quantitative comparison of different GNSS receiver architectures. The results show that no single architecture excels in all cases, and the best choice depends on the actual use case

Information Theory and the Complexity of Boolean Functions

This paper explores the connections between two areas pioneered by Shannon: the transmission of information with a fidelity criterion, and the realization of Boolean functions by networks and formulae. We study three phenomena: The effect of the relative number of O\u27s and l\u27s in a function\u27s table on its complexity. The effect of the number of unspecified entries in a partially specified function\u27s table on its complexity. The effect of the number of errors allowed in the realization of a function on its complexity. Our main result is a precise version of the following statement: The complexity of approximately realizing a partially specified Boolean function, in whose table a fractiond of the entries are unspecified and a fractionp of the specified entries are l\u27swith errors allowed in a fraction not more thane of the specified entries, is less by the factor (1 −d) [H(p) − H(e)] (whereH(z) = −z log2 z −(1 −z) log2 (1 −z) is the binary entropy function) than the complexity of exactly realizing an arbitrary fully specified Boolean function. We also give an intuitively appealing information-theoretic interpretation of the result