Architecture, design, and modeling of the OPSnet asynchronous optical packet switching node

An all-optical packet-switched network supporting multiple services represents a long-term goal for network operators and service providers alike. The EPSRC-funded OPSnet project partnership addresses this issue from device through to network architecture perspectives with the key objective of the design, development, and demonstration of a fully operational asynchronous optical packet switch (OPS) suitable for 100 Gb/s dense-wavelength-division multiplexing (DWDM) operation. The OPS is built around a novel buffer and control architecture that has been shown to be highly flexible and to offer the promise of fair and consistent packet delivery at high load conditions with full support for quality of service (QoS) based on differentiated services over generalized multiprotocol label switching

Parallel Desynchronized Block Matching: A Feasible Scheduling Algorithm for the Input-Buffered Wavelength-Routed Switch

The input-buffered wavelength-routed (IBWR) switch is a promising switching architecture for slotted optical packet switching (OPS) networks. The benefits of the IBWR fabric are a better scalability and lower hardware cost, when compared to output buffered OPS proposals. A previous work characterized the scheduling problem of this architecture as a type of matching problem in bipartite graphs. This characterization establishes an interesting relation between the IBWR scheduling and the scheduling of electronic virtual output queuing switches. In this paper, this relation is further explored, for the design of feasible IBWR scheduling algorithms, in terms of hardware implementation and execution time. As a result, the parallel desynchronized block matching (PDBM) algorithm is proposed. The evaluation results presented reveal that IBWR switch performance using the PDBM algorithm is close to the performance bound given by OPS output buffered architectures. The performance gap is especially small for dense wavelength division multiplexing (DWDM) architectures.This research has been funded by the Spanish MCyT grant TEC2004-05622-C04-02/TCM (ARPaq). Authors would like to thank also the COST 291 action and the e-Photon/ONe+ European Network of Excellence

Control Plane Hardware Design for Optical Packet Switched Data Centre Networks

Optical packet switching for intra-data centre networks is key to addressing traffic requirements. Photonic integration and wavelength division multiplexing (WDM) can overcome bandwidth limits in switching systems. A promising technology to build a nanosecond-reconfigurable photonic-integrated switch, compatible with WDM, is the semiconductor optical amplifier (SOA). SOAs are typically used as gating elements in a broadcast-and-select (B\&S) configuration, to build an optical crossbar switch. For larger-size switching, a three-stage Clos network, based on crossbar nodes, is a viable architecture. However, the design of the switch control plane, is one of the barriers to packet switching; it should run on packet timescales, which becomes increasingly challenging as line rates get higher. The scheduler, used for the allocation of switch paths, limits control clock speed. To this end, the research contribution was the design of highly parallel hardware schedulers for crossbar and Clos network switches. On a field-programmable gate array (FPGA), the minimum scheduler clock period achieved was 5.0~ns and 5.4~ns, for a 32-port crossbar and Clos switch, respectively. By using parallel path allocation modules, one per Clos node, a minimum clock period of 7.0~ns was achieved, for a 256-port switch. For scheduler application-specific integrated circuit (ASIC) synthesis, this reduces to 2.0~ns; a record result enabling scalable packet switching. Furthermore, the control plane was demonstrated experimentally. Moreover, a cycle-accurate network emulator was developed to evaluate switch performance. Results showed a switch saturation throughput at a traffic load 60\% of capacity, with sub-microsecond packet latency, for a 256-port Clos switch, outperforming state-of-the-art optical packet switches

Knockout packet loss probability analysis of SCWP optical packet switching wavelength distributed knockout architecture

The deployment of Optical Packet Switching (OPS) in Dense Wavelength Division Multiplexing (DWDM) backbone networks is perceived as a medium term promising alternative. Scalability restrictions imply that conventional switching architectures are unfeasible in this large-scale scenario. In a previous paper, the wavelength-distributed knockout architecture was proposed as a cost-effective scaling strategy for OPS switching fabrics. In this paper, this growable architecture is applied to OPS switching fabrics able to emulate output buffering. We also propose an scheduling algorithm which provides optimum performance if knockout packet losses are made negligible. The mathematical analysis to evaluate the knockout packet loss probability of this architecture is obtained, under uniform and non-uniform traffic patterns. To complement the switch dimensioning process, an upper bound assuring 0-knockout packet losses is compared with the exact analytical results.This research has been funded by Spanish MCyT grants TEC2004-05622-C04-01/TCM (CAPITAL) and TEC2004-05622-C04-02/TCM (ARPaq) and Xunta de Galicia grant PGIDIT04TIC322003PR

A Priority Based Optical Header Contention Resolution in Optical Burst Switching Networks

OBS is a promising switching paradigm for the next-generation Internet.In OBS, data packets are assembled into variable size data burst which are transmitted optically over Dense Wavelength Division Multiplexing(DWDM)networks without O/E/O conversion. The control packet is sent before the data burst to reserve resources and configure switches along the path .The control packet is sent along the separate control channel and goes through O/E/O conversion. We have discussed various OBS signalling protocols and Burst Scheduling Algorithms. As the data channel bandwidth will grow it will lead to the overloading of the control path. In this thesis we have proposed an algorithm to resolve the contention of the optical header. The algorithm assigns the priority to each control packet arriving at the same time .The control packet with highest priority is selected for processing. Simulation results have shown that the technique is effective in improving the throughput