A Second-Order ΣΔ ADC using sputtered IGZO TFTs with multilayer dielectric

This dissertation combines materials science and electronics engineering to implement, for the first time, a 2nd-order ∑∆ ADC using oxide TFTs. The transistors employ a sputtered IGZO semiconductor and an optimizeddielectric layer, based on mixtures of sputtered Ta2O5and SiO2. These dielectrics are studied in multilayer configurations, being the best results achieved for 7 layers: IG7.5 MV/cm, while keeping κ>10, yielding a major improvement over Ta2O5single-layer. After annealing at 200 °C, TFTs with these dielectrics exhibit μSAT≈13 cm2/Vs, On/Off≈107and S≈0.2 V/dec. An a-Si:H TFT RPI model is adapted to simulate these devices with good fitting to experimental data. Concerning circuits, the ∑∆ architecture is naturally selected to deal with device mismatch. After design optimization, ADC simulations achieve SNDR≈57 dB, DR≈65 dB and power dissipation, approximately, of 22 mW (VDD=10 V), which are above the current state-of-the-art for competing thinfilm technologies, such as organics or even LTPS. Mask layouts are currently under verification to enable successful circuit fabrication in the next months.This work is a major step towards the design of complex multifunctional electronic systems with oxide TFT technology, being integrated in ongoing EU-funded and FCT-funded research projects at CENIMAT and UNINOVA

Insulators for 2D nanoelectronics: the gap to bridge

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators

Low-temperature amorphous oxide semiconductors for thin-film transistors and memristors: physical insights and applications

While amorphous oxides semiconductors (AOS), namely InGaZnO (IGZO), have found market application in the display industry, their disruptive properties permit to envisage for more advanced concepts such as System-on-Panel (SoP) in which AOS devices could be used for addressing (and readout) of sensors and displays, for communication, and even for memory as oxide memristors are candidates for the next-generation memories. This work concerns the application of AOS for these applications considering the low thermal budgets (< 180 °C) required for flexible, low cost and alternative substrates. For maintaining low driving voltages, a sputtered multicomponent/multi-layered high-κ dielectric (Ta2O5+SiO2) was developed for low temperature IGZO TFTs which permitted high performance without sacrificing reliability and stability. Devices’ performance under temperature was investigated and the bias and temperature dependent mobility was modelled and included in TCAD simulation. Even for IGZO compositions yielding very high thermal activation, circuit topologies for counteracting both this and the bias stress effect were suggested. Channel length scaling of the devices was investigated, showing that operation for radio frequency identification (RFID) can be achieved without significant performance deterioration from short channel effects, which are attenuated by the high-κ dielectric, as is shown in TCAD simulation. The applicability of these devices in SoP is then exemplified by suggesting a large area flexible radiation sensing system with on-chip clock-generation, sensor matrix addressing and signal read-out, performed by the IGZO TFTs. Application for paper electronics was also shown, in which TCAD simulation was used to investigate on the unconventional floating gate structure. AOS memristors are also presented, with two distinct operation modes that could be envisaged for data storage or for synaptic applications. Employing typical TFT methodologies and materials, these are ease to integrate in oxide SoP architectures

Copper Metal for Semiconductor Interconnects

Resistance-capacitance (RC) delay produced by the interconnects limits the speed of the integrated circuits from 0.25 mm technology node. Copper (Cu) had been used to replace aluminum (Al) as an interconnecting conductor in order to reduce the resistance. In this chapter, the deposition method of Cu films and the interconnect fabrication with Cu metallization are introduced. The resulting integration and reliability challenges are addressed as well

Study Of Nanoscale Cmos Device And Circuit Reliability

The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices from device level to circuit level; The more real voltage stress case high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future

Nano-engineering and Simulating Electrostatic Capacitors for Electrical Energy Storage

Electrical energy storage solutions with significantly higher gravimetric and volumetric energy densities and rapid response rates are needed to balance the highly dynamic, time-variant supply and demand for power. Nanoengineering can provide useful structures for electrical energy storage because it offers the potential to increase efficiency, reduce size/weight, and improve performance. While several nanostructured devices have shown improvements in energy and/or power densities, this dissertation focuses on the nanoengineering of electrostatic capacitors (ESC) and application of these high-power electrostatic capacitors in electrical energy storage systems. A porous nano-template with significant area enhancement per planar unit area coated with ultra-thin metal-insulator-metal (MIM) layers has shown significant improvements in areal capacitance. However, sharp asperities inherent to the initial nano-template localized electric fields and caused premature (low field) breakdown, limiting the possible energy density (E = ½ CV2/m). A nanoengineering strategy was identified for rounding the template asperities, and this showed a significant increase in the electrical breakdown strength of the device, providing rapid charging and discharging and an energy density of 1.5 W-h/kg - which compares favorably with the best state-of-the-art devices that provide 0.7 W-h/kg. The combination of the high-power ESC with a complementary high-energy-density electrochemical capacitor (ECC) was modeled to evaluate methods resulting in the combined power-energy storage capabilities. While significant improvements in the ESC's energy density were reported, the nanodevices display nonlinear leakage resistance, which directly relates to charge retention. The ECC has distinctly different nonlinearities, but can retain a greater density of charge for significantly longer, albeit with slower inherent charging and discharging rates than the ESC. The experimentally derived dynamic model simulating the nonlinear performance of the ESC and ECC devices indicated this hybrid-circuit reduces the time required to charge the ECC to near-maximum capacity by a factor of up to ~ 12

DESIGN, MODELING, OPTIMIZATION, AND BENCHMARKING OF INTERCONNECTS AND SCALING TECHNOLOGIES AND THEIR CIRCUIT AND SYSTEM LEVEL IMPACT

This research focuses on the future of integrated circuit (IC) scaling technologies at the device and back end of line (BEOL) level. This work includes high level modeling of different technologies and quantifying potential performance gains on a circuit and system level. From the device side, this research looks at the scaling challenges and the future scaling drivers for conventional charge-based devices implemented at the 7nm technology node and beyond. It examines the system-level performance of stacking device logic in addition to tunneling field effect transistors (TFET) and their potential as beyond-CMOS devices. Finally, this research models and benchmarks BEOL scaling challenges and evaluates proposed technological advancements such as metal barrier scaling for copper interconnects and replacing local interconnects with ruthenium. Potential impact on performance, power, and area of these interconnect technologies is quantified for fully placed and routed circuits.Ph.D

Design, Fabrication and Characterization of GaN HEMTs for Power Switching Applications

The unique properties of the III-nitride heterostructure, consisting of gallium nitride (GaN), aluminium nitride (AlN) and their ternary compounds (e.g. AlGaN, InAlN), allow for the fabrication of high electron mobility transistors (HEMTs). These devices exhibit high breakdown fields, high electron mobilities and small parasitic capacitances, making them suitable for wireless communication and power electronic applications. In this work, GaN-based power switching HEMTs and low voltage, short-channel HEMTs were designed, fabricated, and characterized.In the first part of the thesis, AlGaN/GaN-on-SiC high voltage metal-insulator-semiconductor (MIS)HEMTs fabricated on a novel ‘buffer-free’ heterostructure are presented. This heterostructure effectively suppresses buffer-related trapping effects while maintaining high electron confinement and low leakage currents, making it a viable material for high voltage, power electronic HEMTs. This part of the thesis covers device processing techniques to minimize leakage currents and maximize breakdown voltages in these ‘buffer-free’ MISHEMTs. Additionally, a recess-etched, Ta-based, ohmic contact process was utilized to form low-resistive ohmic contacts with contact resistances of 0.44-0.47 Ω∙mm. High voltage operation can be achieved by employing a temperature-stable nitrogen implantation isolation process, which results in three-terminal breakdown fields of 98-123 V/μm. By contrast, mesa isolation techniques exhibit breakdown fields below 85 V/μm and higher off-state leakage currents. Stoichiometric low-pressure chemical vapor deposition (LPCVD) SiNx passivation layers suppress gate currents through the AlGaN barrier below 10 nA/mm over 1000 V, which is more than two orders of magnitude lower compared to Si-rich SiNx passivation layers. A 10% dynamic on-resistance increase at 240 V was measured in HEMTs with stoichiometric SiNx passivation, which is likely caused by slow traps with time constants over 100 ms. SiNx gate dielectrics display better electrical isolation at high voltages compared to HfO2 and Ta2O5. However, the two gate oxides exhibit threshold voltages (Vth) above -2 V, making them a promising alternative for the fabrication of recess-etched normally-off MISHEMTs.Reducing the gate length (Lg) to minimize losses and increase the operating frequency in GaN HEMTs also entails more severe short-channel effects (SCEs), limiting gain, output power and the maximum off-state voltage. In the second part of the thesis, SCEs were studied in short-channel GaN HEMTs using a drain-current injection technique (DCIT). The proposed method allows Vth to be obtained for a wide range of drain-source voltages (Vds) in one measurement, which then can be used to calculate the drain-induced barrier lowering (DIBL) as a rate-of-change of Vth with respect to Vds. The method was validated using HEMTs with a Fe-doped GaN buffer layer and a C-doped AlGaN back-barrier with thin channel layers. Supporting technology computer-aided design (TCAD) simulations indicate that the large increase in DIBL is caused by buffer leakage. This method could be utilized to optimize buffer design and gate lengths to minimize on-state losses and buffer leakage currents in power switching HEMTs