Ultra Low Power SubThreshold Device Design Using New Ion Implantation Profile

Title from PDF of title page, viewed August 14, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 92-97)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2016One of the important aspects of integrated circuit design is doping profile of a transistor along its length, width and depth. Devices for super-threshold circuit usually employ halo and retrograde doping profiles in the channel to eliminate many unwanted effects like DIBL, short channel effect, threshold variation etc. These effects are always become a serious issue whenever circuit operates at higher supply voltage. Subthreshold circuit operates at lower supply voltage and these kind of effects will not be a serious issue. Since subthreshold circuit will operate at much lower supply voltage then devices for subthreshold circuit does not require halo and retrograde doping profiles. This will reduce the number of steps in the fabrication process, the parasitic capacitance and the substrate noise dramatically. This dissertation introduces four new doping profiles for devices to be used in the ultra low-power subthreshold circuits. The proposed scheme addresses doping variations along all the dimensions (length, width and depth) of the device. Therefore, the approaches are three dimensional (3D) in nature. This new doping scheme proposes to employ Gaussian distribution of doping concentration along the length of the channel with highest concentration at the middle of the channel. The doping concentration across the depth of the device from the channel region towards the bulk of the device can follow one of the following four distributions: (a) exponentially decreasing, (b) Gaussian, (c) low to high, and (d) uniform doping. The proposed doping scheme keeps the doping concentration along the width of the device uniform. Therefore, under this scheme we achieve four sets of new 3D doping profiles. This dissertation also introduces a new comprehensive doping scheme for the transistors in subthreshold circuits. The proposed doping scheme would bring doping changes in the source and drain areas along with the substrate and channel region of the transistors. The proposed doping scheme is characterized by the absence of halos at the source and drain end. We propose a Gaussian doping distribution inside the source, drain region and a low-high-low distribution across the depth of the transistor from the channel surface towards the body region. It also has a low-high-low doping distribution along the length of the transistor below the channel region. Results show that a device optimized with proposed doping profiles would offer higher ON current in the subthreshold region than a device with the conventional halo and retrograde doping profiles. Among the four 3D doping profiles for subthreshold device some has better ON current than others. Based on specific requirements one of these four doping profiles can be adopted for different ultra-low-power applications. Our analysis shows better subthreshold swing can be achieved using new doping profile based subthreshold design. Results also show that the optimized device with the proposed comprehensive doping profile would provide higher ON current (Iₒₙ) at smaller body bias condition. The analysis is performed by changing the doping profile, body bias and (Vgs) to observe the off-state current (Iₒff), threshold voltage variation, magnitude of Iₒₙ/Iₒff ratio, transconductance and the output conductance with the proposed doping profiles.Introduction -- Subthreshold background -- Implantation profiles -- Threshold voltage calculation -- Comprehensive implantation profile -- Conclusion and future workxvi, 98 page

Multigate MOSFETs for digital performance and high linearity, and their fabrication techniques

The aggressive downscaling of complementary metal–oxide–semiconductor (CMOS) technology is facing great challenges to overcome severe short-channel effects. Multigate MOSFETs are one of the most promising candidates for scaling beyond Si CMOS, due to better electrostatic control as compared to conventional planar MOSFETs. Conventional dry etching-induced surface damage is one of the main sources of performance degradation for multigate transistors, especially for III-V high mobility materials. It is also challenging to increase the fin aspect ratio by dry etching because of the non-ideal anisotropic etching profile. Here, we report a novel method, inverse metal-assisted chemical etching (i-MacEtch), in lieu of conventional RIE etching, for 3D fin channel formation. InP junctionless FinFETs with record high-aspect-ratio (~ 50:1) fins are demonstrated by this method for the first time. The i-MacEtch process flow eliminates dry-etching-induced plasma damage, high energy ion implantation damage, and high temperature annealing, allowing for the fabrication of InP fin channels with atomically smooth sidewalls. The sidewall features resulting from this unique and simplified process ensure high interface quality between high-k dielectric layer and InP fin channel. Experimental and theoretical analyses show that high-aspect-ratio FinFETs, which could deliver more current per area under much relaxed horizontal geometry requirements, are promising in pushing the technology node ahead where conventional scaling has met its physical limits. The performance of the FinFET was further investigated through numerical simulation. A new kind of FinFET with asymmetric gate and source/drain contacts has been proposed and simulated. By benchmarking with conventional symmetric FinFET, better short-channel behavior with much higher current density is confirmed. The design guidelines are provided. The overall circuit delay can be minimized by optimizing gate lengths according to different local parasites among circuits in interconnection-delay-dominated SoC applications. Continued transistor scaling requires even stronger gate electrostatic control over the channel. The ultimate scaling structure would be gate-all-around nanowire MOSFETs. We demonstrate III-V junctionless gate-all-around (GAA) nanowire (NW) MOSFETs for the first time. For the first time, source/drain (S/D) resistance and thermal budget are minimized by regrowth using metalorganic chemical vapor deposition (MOCVD) in III-V MOSFETs. The fabricated short-channel (Lg=80 nm) GaAs GAA NWFETs with extremely narrow nanowire width (WNW= 9 nm) show excellent transconductance (gm) linearity at biases (300 mV), characterized by the high third intercept point (2.6 dBm). The high linearity is especially important for low power applications because it is insensitive to bias conditions

Simulation of charge-trapping in nano-scale MOSFETs in the presence of random-dopants-induced variability

The growing variability of electrical characteristics is a major issue associated with continuous downscaling of contemporary bulk MOSFETs. In addition, the operating conditions brought about by these same scaling trends have pushed MOSFET degradation mechanisms such as Bias Temperature Instability (BTI) to the forefront as a critical reliability threat. This thesis investigates the impact of this ageing phenomena, in conjunction with device variability, on key MOSFET electrical parameters. A three-dimensional drift-diffusion approximation is adopted as the simulation approach in this work, with random dopant fluctuations—the dominant source of statistical variability—included in the simulations. The testbed device is a realistic 35 nm physical gate length n-channel conventional bulk MOSFET. 1000 microscopically different implementations of the transistor are simulated and subjected to charge-trapping at the oxide interface. The statistical simulations reveal relatively rare but very large threshold voltage shifts, with magnitudes over 3 times than that predicted by the conventional theoretical approach. The physical origin of this effect is investigated in terms of the electrostatic influences of the random dopants and trapped charges on the channel electron concentration. Simulations with progressively increased trapped charge densities—emulating the characteristic condition of BTI degradation—result in further variability of the threshold voltage distribution. Weak correlations of the order of 10-2 are found between the pre-degradation threshold voltage and post-degradation threshold voltage shift distributions. The importance of accounting for random dopant fluctuations in the simulations is emphasised in order to obtain qualitative agreement between simulation results and published experimental measurements. Finally, the information gained from these device-level physical simulations is integrated into statistical compact models, making the information available to circuit designers

A Process Variation Tolerant Self-Compensation Sense Amplifier Design

As we move under the aegis of the Moore\u27s law, we have to deal with its darker side with problems like leakage and short channel effects. Once we go beyond 45nm regime process variations also have emerged as a significant design concern.Embedded memories uses sense amplifier for fast sensing and typically, sense amplifiers uses pair of matched transistors in a positive feedback environment. A small difference in voltage level of applied input signals to these matched transistors is amplified and the resulting logic signals are latched. Intra die variation causes mismatch between the sense transistors that should ideally be identical structures. Yield loss due to device and process variations has never been so critical to cause failure in circuits. Due to growth in size of embedded SRAMs as well as usage of sense amplifier based signaling techniques, process variations in sense amplifiers leads to significant loss of yield for that we need to come up with process variation tolerant circuit styles and new devices. In this work impact of transistor mismatch due to process variations on sense amplifier is evaluated and this problem is stated. For the solution of the problem a novel self compensation scheme on sense amplifiers is presented on different technology nodes up to 32nm on conventional bulk MOSFET technology. Our results show that the self compensation technique in the conventional bulk MOSFET latch type sense amplifier not just gives improvement in the yield but also leads to improvement in performance for latch type sense amplifiers. Lithography related CD variations, fluctuations in dopant density, oxide thickness and parametric variations of devices are identified as a major challenge to the classical bulk type MOSFET. With the emerging nanoscale devices, SIA roadmap identifies FinFETs as a candidate for post-planar end-of-roadmap CMOS device. With current technology scaling issues and with conventional bulk type MOSFET on 32nm node our technique can easily be applied to Double Gate devices. In this work, we also develop the model of Double Gate MOSFET through 3D Device Simulator Damocles and TCAD simulator. We propose a FinFET based process variation tolerant sense amplifier design that exploits the back gate of FinFET devices for dynamic compensation against process variations. Results from statistical simulation show that the proposed dynamic compensation is highly effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

A statistical study of time dependent reliability degradation of nanoscale MOSFET devices

Charge trapping at the channel interface is a fundamental issue that adversely affects the reliability of metal-oxide semiconductor field effect transistor (MOSFET) devices. This effect represents a new source of statistical variability as these devices enter the nano-scale era. Recently, charge trapping has been identified as the dominant phenomenon leading to both random telegraph noise (RTN) and bias temperature instabilities (BTI). Thus, understanding the interplay between reliability and statistical variability in scaled transistors is essential to the implementation of a ‘reliability-aware’ complementary metal oxide semiconductor (CMOS) circuit design. In order to investigate statistical reliability issues, a methodology based on a simulation flow has been developed in this thesis that allows a comprehensive and multi-scale study of charge-trapping phenomena and their impact on transistor and circuit performance. The proposed methodology is accomplished by using the Gold Standard Simulations (GSS) technology computer-aided design (TCAD)-based design tool chain co-optimization (DTCO) tool chain. The 70 nm bulk IMEC MOSFET and the 22 nm Intel fin-shape field effect transistor (FinFET) have been selected as targeted devices. The simulation flow starts by calibrating the device TCAD simulation decks against experimental measurements. This initial phase allows the identification of the physical structure and the doping distributions in the vertical and lateral directions based on the modulation in the inversion layer’s depth as well as the modulation of short channel effects. The calibration is further refined by taking into account statistical variability to match the statistical distributions of the transistors’ figures of merit obtained by measurements. The TCAD simulation investigation of RTN and BTI phenomena is then carried out in the presence of several sources of statistical variability. The study extends further to circuit simulation level by extracting compact models from the statistical TCAD simulation results. These compact models are collected in libraries, which are then utilised to investigate the impact of the BTI phenomenon, and its interaction with statistical variability, in a six transistor-static random access memory (6T-SRAM) cell. At the circuit level figures of merit, such as the static noise margin (SNM), and their statistical distributions are evaluated. The focus of this thesis is to highlight the importance of accounting for the interaction between statistical variability and statistical reliability in the simulation of advanced CMOS devices and circuits, in order to maintain predictivity and obtain a quantitative agreement with a measured data. The main findings of this thesis can be summarised by the following points: Based on the analysis of the results, the dispersions of VT and ΔVT indicate that a change in device technology must be considered, from the planar MOSFET platform to a new device architecture such as FinFET or SOI. This result is due to the interplay between a single trap charge and statistical variability, which has a significant impact on device operation and intrinsic parameters as transistor dimensions shrink further. The ageing process of transistors can be captured by using the trapped charge density at the interface and observing the VT shift. Moreover, using statistical analysis one can highlight the extreme transistors and their probable effect on the circuit or system operation. The influence of the passgate (PG) transistor in a 6T-SRAM cell gives a different trend of the mean static noise margin

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

Variability-Aware Design of Subthreshold Devices

Over the last 10 years, digital subthreshold logic circuits have been developed for applications in the ultra-low power design domain, where performance is not the priority. Recently, devices optimized for subthreshold operation have been introduced as potential construction blocks. However, for these devices, a strong sensitivity to process variations is expected due to the exponential relationship of the subthreshold drive current and the threshold voltage. In this thesis, a yield optimization technique is proposed to suppress the variability of a device optimized for subthreshold operation. The goal of this technique is to construct and inscribe a maximum yield cube in the 3-D feasible region composed of oxide thickness, gate length, and channel doping concentration. The center of this cube is chosen as the maximum yield design point with the highest immunity against variations. By using the technique, a transistor is optimized for subthreshold operation in terms of the desired total leakage current and intrinsic delay bounds. To develop the concept of the technique, sample devices are designed for 90nm and 65nm technologies. Monte Carlo simulations verify the accuracy of the technique for meeting power and delay constraints under technology-specific variances of the design parameters of the device

A test structure for the measurement and characterization of layout-induced transistor variation

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student-submitted PDF version of thesis.Includes bibliographical references (p. 131-139).Transistor scaling has enabled us to design circuits with higher performance, lower cost, and higher density; billions of transistors can now be integrated onto a single die. However, this trend also magnifies the significance of device variability. In this thesis, we focus on the study of layout-induced systematic variation. Specifically, we investigate how pattern densities can affect transistor behavior. Two pattern densities are chosen in our design: polysilicon density and shallow-trench isolation (STI) density. A test structure is designed to study the systematic spatial dependency between transistors in order to determine the impact of different variation sources on transistor characteristics and understand the radius of influence that defines the neighborhood of shapes which play a part in determining the transistor characteristics. A more accurate transistor model based on surrounding layout details can be built using these results. The test structure is divided into six blocks, each having a different polysilicon density or STI density. A rapid change of pattern density between blocks is designed to emulate a step response for future modeling. The two pattern densities are chosen to reflect the introduction of new process technologies, such as strain engineering and rapid thermal annealing. The test structure is designed to have more than 260K devices under test (DUT). In addition to the changes in pattern density, the impact of transistor sizing, number of polysilicon fingers, finger spacing, and active area are also explored and studied in this thesis. Two different test circuits are designed to perform the measurement.(cont.) The first test circuit is designed to work with of-chip wafer probe testing equipment; the second test circuit is designed to have on-chip current measurement capabilities using a high dynamic range analog-to-digital converter (ADC). The ADC has a dynamic range of over four orders of magnitude to measure currents from 50nA to 1mA. The test chip also implements a hierarchical design with a minimum amount of peripheral circuitry, so that most of the chip area is dedicated for the transistors under test.by Albert Hsu Ting Chang.S.M

Ultra-Low Power Ternary CMOS Platform for Physical Synthesis of Multi-Valued Logic and Memory Applications

Department of Electrical EngineeringMotivation of this work is to provide feasible, scalable, and designable multi-valued logic (MVL) device platform for physical synthesis of MVL circuits. Especially, ternary device and its general logic functions are focused, owing to most efficiently reduced circuit complexity per radix (R) increase. By designing the OFF-state constant current, not only the standby power (PS) issue of additional intermediate state is overcome, but also continuous supply voltage (VDD) scaling and dynamic power (PD) scaling are possible owing to single-step I-V characteristics. By applying a novel ternary device concept to CMOS technology with OFF-state current mechanism of band-to-band tunneling (BTBT) currents (IBTBT) and subthreshold diffusion current (Isub), the logic changes from binary to ternary are confirmed using mixed-mode device simulation. I experimentally demonstrate ternary CMOS (T-CMOS) and verified its low-power standard ternary inverter (STI) operation by designing channel profiles in conventional binary CMOS. The realized complementary ternary n/pMOS (T-n/pMOS) have fully gate bias (VG)-independent and symmetrical IBTBT of ~10 pA/???m based on proven ion-implantation process, which produces stable and designable intermediate state (VOM) at exactly VDD/2. To present T-CMOS design frameworks in terms of static noise margin (SNM) enhancement and ultra-low power operation, I develop the compact model of T-CMOS and verify the physical model parameters with experimental data. Through the feasible design of Isub with abrupt channel profile based on low thermal budget process, STI has a SNM of 283 mV (80 % of ideal SNM) at VDD= 1V operation and intermediate state stability of ??VOM < ?? 0.1V, even considering the random-dopant fluctuation (RDF) of 32 nm and 22 nm technology. Continuous VDD scaling below 0.5V (SNM= 40% at VDD = 0.3V) enables STI operation with ultra-low PD and PS based on exponentially reduced IBTBT currents. As MVL and memory (MVM) applications, minimum(MIN)/maximum(MAX) gates, analog-to-digital converter (ADC) circuit, and 5-state latch are studied with T-CMOS compact model. Especially ADC circuits revolutionary decreases number of device and circuit interconnection with 9.6% area of binary system.ope