Computational Design of Wiring Layout on Tight Suits with Minimal Motion Resistance

An increasing number of electronics are directly embedded on the clothing to monitor human status (e.g., skeletal motion) or provide haptic feedback. A specific challenge to prototype and fabricate such a clothing is to design the wiring layout, while minimizing the intervention to human motion. We address this challenge by formulating the topological optimization problem on the clothing surface as a deformation-weighted Steiner tree problem on a 3D clothing mesh. Our method proposed an energy function for minimizing strain energy in the wiring area under different motions, regularized by its total length. We built the physical prototype to verify the effectiveness of our method and conducted user study with participants of both design experts and smart cloth users. On three types of commercial products of smart clothing, the optimized layout design reduced wire strain energy by an average of 77% among 248 actions compared to baseline design, and 18% over the expert design.Comment: This work is accepted at SIGGRAPH ASIA 2023(Conference Track

Automated Placement Of A Transistor Pair For Analogue

The performances of analogue circuits are affected by surrounding parameters such as levels of noise, thermal gradients of a circuit, and parasitic effects from both resistive and capacitive part. As there are no effective approaches to handle these analogue constraints as mentioned above, the focuses to develop IC design tools are bended towards digital circuits. The purpose of this research is to introduce a complete methodology for transistor pair placement for analogue layout using a concept of cells and arrays based on migration and reuse. The entire process consists of Standard Cell Generation to produce standard cell for analogue circuits, Matching Generator with array alignment to generate transistor matching of common-centroid arrangement, and Auto Routing for global routing. The methodology is translated into automation by a graphical user interface to render a fully functional layout designs in a few steps and fraction of time. This research describes such a system in obtaining a layout that can be configured like a set of building blocks that meets all design specifications. In comparison to all the different approaches that have been discussed and analysed prior to this research, a new design flow for analogue layout combined with automation is constructed by considering transistor matching as a constraint

One way Doppler extractor. Volume 1: Vernier technique

A feasibility analysis, trade-offs, and implementation for a One Way Doppler Extraction system are discussed. A Doppler error analysis shows that quantization error is a primary source of Doppler measurement error. Several competing extraction techniques are compared and a Vernier technique is developed which obtains high Doppler resolution with low speed logic. Parameter trade-offs and sensitivities for the Vernier technique are analyzed, leading to a hardware design configuration. A detailed design, operation, and performance evaluation of the resulting breadboard model is presented which verifies the theoretical performance predictions. Performance tests have verified that the breadboard is capable of extracting Doppler, on an S-band signal, to an accuracy of less than 0.02 Hertz for a one second averaging period. This corresponds to a range rate error of no more than 3 millimeters per second

A design flow for performance planning : new paradigms for iteration free synthesis

In conventional design, higher levels of synthesis produce a netlist, from which layout synthesis builds a mask specification for manufacturing. Timing anal ysis is built into a feedback loop to detect timing violations which are then used to update specifications to synthesis. Such iteration is undesirable, and for very high performance designs, infeasible. The problem is likely to become much worse with future generations of technology. To achieve a non-iterative design flow, early synthesis stages should use wire planning to distribute delays over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays

A survey and taxonomy of layout compaction algorithms

This paper presents a survey and a taxonomy of layout compaction algorithms, which are an essential part of modern symbolic layout tools employed in VLSI circuit design. Layout compaction techniques are also used in the low-end stages of silicon compilation tools and module generators. The paper addresses the main algorithms used in compaction, focusing on their implementation characteristics, performance, advantages and drawbacks. Compaction is a highly important operation to optimize the use of silicon area, achieve higher speed through wire length minimization, support technology retargeting and also allow the use of legacy layouts. Optimized cells that were developed for a fabrication process with a set of design rules have to be retargeted for a new and more compact process with a different set of design rules