On the Critical Role of Ferroelectric Thickness for Negative Capacitance Device-Circuit Interaction

This paper demonstrates the critical role that Ferroelectric (FE) layer thickness (tFE) plays in Negative Capacitance (NC) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a 14nm FDSOI technology node, exploring the impact of tFE on the figures of merit of n-type and p-type devices, voltage transfer characteristic (VTC) and noise margin of inverter as well as the speed of buffer circuits. First, we analyze the device electrical parameters (e.g., ION, SS, ION/IOFF and Cgg) by varying tFE up to the maximum level at which hysteresis in the I-V characteristic starts. Then, we analyze the deleterious impact of Negative Differential Resistance (NDR), due to the drain to gate coupling, demonstrating how it imposes an additional constraint limiting the maximum tFE. We show the consequences of NDR effects on the VTC and noise margin of inverter, which are essential components for constructing robust clock trees in any chip. We demonstrate how the considerable increase in the gate’s capacitance due to FE seriously degrades the circuit’s performance imposing further constraints limiting the maximum tFE. Further, we analyze the impact of tFE on the SRAM cell static performance metrics such hold noise margin (HNM), read noise margin (RNM) and write noise margin (WNM) at supply voltages of 0.7V and 0.4V. We demonstrate that the HNM and RNM in a NC-FDSOI FET based SRAM cell are higher then those of the baseline FDSOI FET based SRAM cell noise margin and further increase with tFE. However, the WNM in general follows a non monotonic trend w.r.t tFE, and the trend also depends on the supply voltage. Finally, we optimize the design of the SRAM cell considering overall performance metrics. All in all, our analysis provides guidance for device and circuit designers to select the optimal FE thickness for NCFETs in which hysteresis-free operations, reliability, and performance are optimized

Low Leakage and Robust Sub-threshold SRAM Cell using Memristor

This work aims to improve the total power dissipation, leakage currents and stability without disturbing the logic state of SRAM cell with concept called sub-threshold operation. Though, sub-threshold SRAM proves to be advantageous but fails with basic 6T SRAM cell during readability and writability. In this paper we have investigated a non-volatile 6T2M (6 Transistors & 2 Memristors) sub-threshold SRAM cell working at lower supply voltage of VDD=0.3V, where Memristor is used to store the information even at power failures and restores previous data with successful read and write operation overcomes the challenge faced. This paper also proposes a new configuration of non-volatile 6T2M (6 Transistors & 2 Memristors) sub-threshold SRAM cell resulting in improved behaviour in terms of power, stability and leakage current where read and write power has improved by 40% and 90% respectively when compared to 6T2M (conventional) SRAM cell. The proposed 6T2M SRAM cell offers good stability of RSNM=65mV and WSNM=93mV which is much improved at low voltage when compared to conventional basic 6T SRAM cell, and improved leakage current of 4.92nA is achieved as compared

Low Leakage and Robust Sub-threshold SRAM Cell using Memristor

This work aims to improve the total power dissipation, leakage currents and stability without disturbing the logic state of SRAM cell with concept called sub-threshold operation. Though, sub-threshold SRAM proves to be advantageous but fails with basic 6T SRAM cell during readability and writability. In this paper we have investigated a non-volatile 6T2M (6 Transistors & 2 Memristors) sub-threshold SRAM cell working at lower supply voltage of VDD=0.3V, where Memristor is used to store the information even at power failures and restores previous data with successful read and write operation overcomes the challenge faced. This paper also proposes a new configuration of non-volatile 6T2M (6 Transistors & 2 Memristors) sub-threshold SRAM cell resulting in improved behaviour in terms of power, stability and leakage current where read and write power has improved by 40% and 90% respectively when compared to 6T2M (conventional) SRAM cell. The proposed 6T2M SRAM cell offers good stability of RSNM=65mV and WSNM=93mV which is much improved at low voltage when compared to conventional basic 6T SRAM cell, and improved leakage current of 4.92nA is achieved as compared

Subthreshold SRAM Design for Energy Efficient Applications in Nanometric CMOS Technologies

Embedded SRAM circuits are vital components in a modern system on chip (SOC) that can occupy up to 90% of the total area. Therefore, SRAM circuits heavily affect SOC performance, reliability, and yield. In addition, most of the SRAM bitcells are in standby mode and significantly contribute to the total leakage current and leakage power consumption. The aggressive demand in portable devices and billions of connected sensor networks requires long battery life. Therefore, careful design of SRAM circuits with minimal power consumption is in high demand. Reducing the power consumption is mainly achieved by reducing the power supply voltage in the idle mode. However, simply reducing the supply voltage imposes practical limitations on SRAM circuits such as reduced static noise margin, poor write margin, reduced number of cells per bitline, and reduced bitline sensing margin that might cause read/write failures. In addition, the SRAM bitcell has contradictory requirements for read stability and writability. Improving the read stability can cause difficulties in a write operation or vice versa. In this thesis, various techniques for designing subthreshold energy-efficient SRAM circuits are proposed. The proposed techniques include improvement in read margin and write margin, speed improvement, energy consumption reduction, new bitcell architecture and utilizing programmable wordline boosting. A programmable wordline boosting technique is exploited on a conventional 6T SRAM bitcell to improve the operational speed. In addition, wordline boosting can reduce the supply voltage while maintaining the operational frequency. The reduction of the supply voltage allows the memory macro to operate with reduced power consumption. To verify the design, a 16-kb SRAM was fabricated using the TSMC 65 nm CMOS technology. Measurement results show that the maximum operational frequency increases up to 33.3% when wordline boosting is applied. Besides, the supply voltage can be reduced while maintaining the same frequency. This allows reducing the energy consumption to be reduced by 22.2%. The minimum energy consumption achieved is 0.536 fJ/b at 400 mV. Moreover, to improve the read margin, a 6T bitcell SRAM with a PMOS access transistor is proposed. Utilizing a PMOS access transistor results in lower zero level degradation, and hence higher read stability. In addition, the access transistor connected to the internal node holding V DD acts as a stabilizer and counterbalances the effect of zero level degradation. In order to improve the writability, wordline boosting is exploited. Wordline boosting also helps to compensate for the lower speed of the PMOS access transistor compared to a NMOS transistor. To verify our design, a 2kb SRAM is fabricated in the TSMC 65 nm CMOS technology. Measurement results show that the maximum operating frequency of the test chip is at 3.34 MHz at 290 mV. The minimum energy consumption is measured as 1.1 fJ/b at 400 mV

Design and Implementation of Low Power SRAM Using Highly Effective Lever Shifters

The explosive growth of battery-operated devices has made low-power design a priority in recent years. In high-performance Systems-on-Chip, leakage power consumption has become comparable to the dynamic component, and its relevance increases as technology scales. These trends are even more evident for SRAM memory devices since they are a dominant source of standby power consumption in low-power application processors. The on-die SRAM power consumption is particularly important for increasingly pervasive mobile and handheld applications where battery life is a key design and technology attribute. In the SRAM-memory design, SRAM cells also comprise the most significant portion of the total chip. Moreover, the increasing number of transistors in the SRAM memories and the MOSs\u27 increasing leakage current in the scaled technologies have turned the SRAM unit into a power-hungry block for both dynamic and static viewpoints. Although the scaling of the supply voltage enables low-power consumption, the SRAM cells\u27 data stability becomes a major concern. Thus, the reduction of SRAM leakage power has become a critical research concern. To address the leakage power consumption in high-performance cache memories, a stream of novel integrated circuit and architectural level techniques are proposed by researchers including leakage-current management techniques, cell array leakage reduction techniques, bitline leakage reduction techniques, and leakage current compensation techniques. The main goal of this work was to improve the cell array leakage reduction techniques in order to minimize the leakage power for SRAM memory design in low-power applications. This study performs the body biasing application to reduce leakage current as well. To adjust the NMOSs\u27 threshold voltage and consequently leakage current, a negative DC voltage could be applied to their body terminal as a second gate. As a result, in order to generate a negative DC voltage, this study proposes a negative voltage reference that includes a trimming circuit and a negative level shifter. These enhancements are employed to a 10kb SRAM memory operating at 0.3V in a 65nm CMOS process

Strain integration and performance optimization in sub-20nm FDSOI CMOS technology

La technologie CMOS à base de Silicium complètement déserté sur isolant (FDSOI) est considérée comme une option privilégiée pour les applications à faible consommation telles que les applications mobiles ou les objets connectés. Elle doit cela à son architecture garantissant un excellent comportement électrostatique des transistors ainsi qu'à l'intégration de canaux contraints améliorant la mobilité des porteurs. Ce travail de thèse explore des solutions innovantes en FDSOI pour nœuds 20nm et en deçà, comprenant l'ingénierie de la contrainte mécanique à travers des études sur les matériaux, les dispositifs, les procédés d'intégration et les dessins des circuits. Des simulations mécaniques, caractérisations physiques (µRaman), et intégrations expérimentales de canaux contraints (sSOI, SiGe) ou de procédés générant de la contrainte (nitrure, fluage de l'oxyde enterré) nous permettent d'apporter des recommandations pour la technologie et le dessin physique des transistors en FDSOI. Dans ce travail de thèse, nous avons étudié le transport dans les dispositifs à canal court, ce qui nous a amené à proposer une méthode originale pour extraire simultanément la mobilité des porteurs et la résistance d'accès. Nous mettons ainsi en évidence la sensibilité de la résistance d'accès à la contrainte que ce soit pour des transistors FDSOI ou nanofils. Nous mettons en évidence et modélisons la relaxation de la contrainte dans le SiGe apparaissant lors de la gravure des motifs et causant des effets géométriques (LLE) dans les technologies FDSOI avancées. Nous proposons des solutions de type dessin ainsi que des solutions technologiques afin d'améliorer la performance des cellules standard digitales et de mémoire vive statique (SRAM). En particulier, nous démontrons l'efficacité d'une isolation duale pour la gestion de la contrainte et l'extension de la capacité de polarisation arrière, qui un atout majeur de la technologie FDSOI. Enfin, la technologie 3D séquentielle rend possible la polarisation arrière en régime dynamique, à travers une co-optimisation dessin/technologie (DTCO).The Ultra-Thin Body and Buried oxide Fully Depleted Silicon On Insulator (UTBB FDSOI) CMOS technology has been demonstrated to be highly efficient for low power and low leakage applications such as mobile, internet of things or wearable. This is mainly due to the excellent electrostatics in the transistor and the successful integration of strained channel as a carrier mobility booster. This work explores scaling solutions of FDSOI for sub-20nm nodes, including innovative strain engineering, relying on material, device, process integration and circuit design layout studies. Thanks to mechanical simulations, physical characterizations and experimental integration of strained channels (sSOI, SiGe) and local stressors (nitride, oxide creeping, SiGe source/drain) into FDSOI CMOS transistors, we provide guidelines for technology and physical circuit design. In this PhD, we have in-depth studied the carrier transport in short devices, leading us to propose an original method to extract simultaneously the carrier mobility and the access resistance and to clearly evidence and extract the strain sensitivity of the access resistance, not only in FDSOI but also in strained nanowire transistors. Most of all, we evidence and model the patterning-induced SiGe strain relaxation, which is responsible for electrical Local Layout Effects (LLE) in advanced FDSOI transistors. Taking into account these geometrical effects observed at the nano-scale, we propose design and technology solutions to enhance Static Random Access Memory (SRAM) and digital standard cells performance and especially an original dual active isolation integration. Such a solution is not only stress-friendly but can also extend the powerful back-bias capability, which is a key differentiating feature of FDSOI. Eventually the 3D monolithic integration can also leverage planar Fully-Depleted devices by enabling dynamic back-bias owing to a Design/Technology Co-Optimization

Improving Phase Change Memory (PCM) and Spin-Torque-Transfer Magnetic-RAM (STT-MRAM) as Next-Generation Memories: A Circuit Perspective

In the memory hierarchy of computer systems, the traditional semiconductor memories Static RAM (SRAM) and Dynamic RAM (DRAM) have already served for several decades as cache and main memory. With technology scaling, they face increasingly intractable challenges like power, density, reliability and scalability. As a result, they become less appealing in the multi/many-core era with ever increasing size and memory-intensity of working sets. Recently, there is an increasing interest in using emerging non-volatile memory technologies in replacement of SRAM and DRAM, due to their advantages like non-volatility, high device density, near-zero cell leakage and resilience to soft errors. Among several new memory technologies, Phase Change Memory (PCM) and Spin-Torque-Transfer Magnetic-RAM (STT-MRAM) are most promising candidates in building main memory and cache, respectively. However, both of them possess unique limitations that preventing them from being effectively adopted. In this dissertation, I present my circuit design work on tackling the limitations of PCM and STT-MRAM. At bit level, both PCM and STT-MRAM suffer from excessive write energy, and PCM has very limited write endurance. For PCM, I implement Differential Write to remove large number of unnecessary bit-writes that do not alter the stored data. It is then extended to STT-MRAM as Early Write Termination, with specific optimizations to eliminate the overhead of pre-write read. At array level, PCM enjoys high density but could not provide competitive throughput due to its long write latency and limited number of read/write circuits. I propose a Pseudo-Multi-Port Bank design to exploit intra-bank parallelism by recycling and reusing shared peripheral circuits between accesses in a time-multiplexed manner. On the other hand, although STT-MRAM features satisfactory throughput, its conventional array architecture is constrained on density and scalability by the pitch of the per-column bitline pair. I propose a Common-Source-Line Array architecture which uses a shared source-line along the row, essentially leaving only one bitline per column. For these techniques, I provide circuit level analyses as well as architecture/system level and/or process/device level discussions. In addition, relevant background and work are thoroughly surveyed and potential future research topics are discussed, offering insights and prospects of these next-generation memories