An Ultra Low Power Digital to Analog Converter Optimized for Small Format LCD Applications

Liquid crystal displays (LCDs) for mobile applications present a unique design challenge. These small format displays can be found primarily in cell phones and PDAs which are devices that have particularly stringent power requirements. At the same time, the displays are increasing in resolution with every generation. This is creating demand for new LCD display technologies. The predominant amorphous thin film transistor technology is no longer feasible in the new high resolution small format screens due to the fact that the displays require too many connections to the driver and the aperture ratios do not allow high density displays. New technologies such as low temperature polysilicon (LTPS) displays continue to shrink in size and increase in resolution. LTPS technology enables the display manufacturer to create relatively high quality transistors on the glass. This allows for a display architecture which integrates the gate driver on the glass. Newer LTPS LCDs also enable a high level of multiplexing the sources lines on the glass which allows for a much simpler connection to the display driver chip. The electronic drivers for these display applications must adhere to strict power and area budgets. This work describes a low-power, area efficient, scalable, digital-to-analog conversion (DAC) integrated circuit architecture optimized for driving small format LCDs. The display driver is based on a twelve channel, 9-bit DAC driver. This architecture, suitable for % VGA resolution displays, exhibited a 2 MSPS conversion rate, less than 300 pW power dissipation per channel using a 5 V supply, and a die area of 0.042 mm per DAC. A new performance standard is set for DAC display drivers in joules per bit areal density

A synchronised Direct Digital Synthesiser

We describe a Direct Digital Synthesiser (DDS) which provides three frequency-locked synchronised outputs to generate frequencies from DC to 160 MHz. Primarily designed for use in a heterodyning range imaging system, the flexibility of the design allows its use in a number of other applications which require any number of stable, synchronised high frequency outputs. Frequency tuning of 32 bit length provides 0.1 Hz resolution when operating at the maximum clock rate of 400 MSPS, while 14 bit phase tuning provides 0.4 mrad resolution. The DDS technique provides very high relative accuracy between outputs, while the onboard oscillator’s stability of ±1 ppm adds absolute accuracy to the design

Performance enhancement techniques for operational amplifiers

Operational amplifiers (op amps) are one of the most fundamental and widely used building blocks for analog and mixed-signal circuits and systems. As transistors’ feature size scales down in the deep submicron process, the short channel effects, high leakage current and reduced supply voltages make the design of op amps more challenging. In this dissertation, we present several methods to improve op amps’ DC gain, slew rate, power efficiency and current utilization efficiency (CUE). A basic requirement for an op amp is high DC gain especially for high precision applications. We introduce a method to robustly improve op amps’ DC gain with negligible power and area overhead. The new DC gain enhancement method can be implemented based on the source degeneration circuit (SDC) or the flipped voltage attenuator (FVA). Compared to the FVA-based technique, the SDC-based technique is more suitable for those CMOS processes whose transistors’ threshold voltages are too low for the transistors in the FVA to work in weak or strong inversion regions. Otherwise, the FVA-based technique is recommended as this technique is more robust to devices’ random mismatch. A prototype op amp with the FVA-based technique is designed and fabricated in the IBM130nm process. The measurement and simulation results of the prototype verify that the technique largely enhances an op amp’s DC and is very robust over process, voltage and temperature variations. Another important op amp requirement is high slew rate. In this regard, we introduce a method that greatly improves an op amp’s slew rate while still preserving its small signal performance by a well-defined turn-on condition. The performance of the introduced method is discussed in comparison with an existing adaptive biasing method that was widely used to enhance slew rate. The introduced method excels in several aspects. First, unlike the adaptive biasing method which degrades an op amp’ linearity, the introduced method is able to enhance linearity. Second, the proposed method improves an op amp’s slew rate by 2320% (vs. 780% by the adaptive method) with the power and area overhead of 2% and 1.2% (vs. 15% and 35% by the adaptive method). In addition, the proposed method improves the op amp’s total harmonic distortion (THD) by 6dB but the adaptive method degrades the THD by 12dB. The ability to drive large capacitive loads is becoming critical for op amps in emerging applications such as liquid crystal display drivers. In this regard, we introduce a power efficient design of op amps that can drive large capacitive loads. The proposed method decouples the large and small signal performance, eliminates current waste in the preamp stages’ load circuits, and is not sensitive to devices’ random mismatches. Compared to the state-of-the-art methods, our design prototype in a CMOS 180nm process shows largely improved small and large signal figure of merits, equivalent to largely improved power efficiency for given small and large signal performance specifications. Folded cascode amplifier (FCA) is a commonly used architecture for designing op amps, but a significant portion of supply current is wasted in the cascode stage. This not only reduces the current utilization efficiency (CUE), defined as the ratio of an FCA’s tail current to its total supply current, but also degrades the FCA’s gain, noise and offset. In this regard, we introduce a method to dramatically reduce a FCA’s cascode stage current without degrading the FCA’s settling performance. Compared to the existing methods, the proposed method effectively improves not only the CUE but also the settling performance of op amps. Lastly, a prototype FCA, with the proposed performance enhancement techniques of gain, slew rate and CUE, is designed to demonstrate the compatibility of these techniques

Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications

abstract: The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator. Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

A Four-stage Power and Area Efficient OTA with 30 × (400pf – 12nf) Capacitive Load Drive Range

Multistage operational transconductance amplifier (OTA) has been a major research focus as a solution to high DC Gain high Gain Bandwidth and wide voltage swing requirement on sub-micron devices. These system requirements, in addition to ultra-large capacitive load drivability (nF-range load capacitor), are useful in applications including LCD drivers, low dropout (LDO) linear regulators, headphone drivers, etc. The major drawback of multistage OTAs is the stability concerns since each added stage introduces low frequency poles. Numerous compensation schemes for three stage OTAs have been proposed in the past decade with only a few four stage OTA in literature. The proposed design is a four stage OTA which uses an active zero block (AZB) to provide left half plane (LHP) zero to help with phase degradation. AZB is embedded in the second stage ensuring reuse of existing block hence providing area and power savings. This design also uses single miller capacitor in the outer loop which ensures improved speed performance with minimal area overhead. A very reliable slew helper is implemented in this design to help with the large signal performance. The slew helper is only operational in the events slewing and does not affect the small signal performance. The proposed design achieves a DC gain of 114 dB, GBW > 1.77MHz and PM > 46.9⁰ for capacitive load ranging from 400pF–12nF (30x) which is the highest recorded range in literature for these type of compensation. It does this by consuming a total power of 143.5µW and an area of 0.007mm^2

High-Linearity Self-Biased CMOS Current Buffer

A highly linear fully self-biased class AB current buffer designed in a standard 0.18 mu m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48 mu W, features an input resistance as low as 89 Omega, high accuracy in the input-output current ratio and total harmonic distortion (THD) figures lower than -60 dB at 30 mu A amplitude signal and 1 kHz frequency. Robustness was proved through Monte Carlo and corner simulations, and finally validated through experimental measurements, showing that the proposed configuration is a suitable choice for high performance low voltage low power applications

Novel approaches in voltage-follower design

The aim of this research programme was to design and develop novel voltagefollowerslbuffers, suitable for radio frequency (RF) applications. The emphases throughout has been on improving key characteristics, in particular distortion, operating bandwidth, input and output impedances, offset-voltage and power supply demands of the design. The majority of the results of this work have been reported by the author in the technical literature (I] to (6). Initially this research focuses on the investigation of the underlying operating principles of the voltage-follower to provide an in-depth understanding of its operation. This study concentrates on establishing reasons for the poor distortion, low input and high output impedances and increased offset-voltage and confirmed that these designs have inherently poor performance in these parameters. The analysis is carried out using both theoretical modelling and computer simulation, using the wellestablished software package ORCAD PSpice. Despite the availability of high performance computer simulation tools, it becomes apparent that 'hand' calculations in the design process, generally based on DC and small-signal transistor parameters, are essential. Therefore a detailed analysis of the transistor-models used throughout this research is carried out with PSpice data. Using the analytical results of the conventional voltage-follower as a benchmark, various novel circuit techniques investigated. Several new circuits are proposed with respect to improving the previously mentioned key characteristics. The first technique comprises local feedback and single-valued current biasing and 111 consists of emitter-followers exclusively throughout the signal path, keeping the distortion of the input signal to low levels [1 J, (2). The second technique is based on local feedback with double-valued current biasing, increasing somewhat the power dissipation but reducing, notably, the distortion of the configuration [3J, [4J, [5J, [6J. The final technique employs the emitter-followers throughout the signal path in combination with global feedback and double-valued current biasing, which presents significantly better results, on certain parameters, than conventional and existing configurations. It is anticipated that this work will be published in the near future

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a high-speed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step