Ultra-Fast, High-Performance 8x8 Approximate Multipliers by a New Multicolumn 3,3:2 Inexact Compressor and its Derivatives

Multiplier, as a key role in many different applications, is a time-consuming, energy-intensive computation block. Approximate computing is a practical design paradigm that attempts to improve hardware efficacy while keeping computation quality satisfactory. A novel multicolumn 3,3:2 inexact compressor is presented in this paper. It takes three partial products from two adjacent columns each for rapid partial product reduction. The proposed inexact compressor and its derivates enable us to design a high-speed approximate multiplier. Then, another ultra-fast, high-efficient approximate multiplier is achieved utilizing a systematic truncation strategy. The proposed multipliers accumulate partial products in only two stages, one fewer stage than other approximate multipliers in the literature. Implementation results by Synopsys Design Compiler and 45 nm technology node demonstrates nearly 11.11% higher speed for the second proposed design over the fastest existing approximate multiplier. Furthermore, the new approximate multipliers are applied to the image processing application of image sharpening, and their performance in this application is highly satisfactory. It is shown in this paper that the error pattern of an approximate multiplier, in addition to the mean error distance and error rate, has a direct effect on the outcomes of the image processing application.Comment: 21 Pages, 18 Figures, 6 Table

Adjustable compression method for still JPEG images

There are a large number of image processing applications that work with different performance requirements and available resources. Recent advances in image compression focus on reducing image size and processing time, but offer no real-time solutions for providing time/quality flexibility of the resulting image, such as using them to transmit the image contents of web pages. In this paper we propose a method for encoding still images based on the JPEG standard that allows the compression/decompression time cost and image quality to be adjusted to the needs of each application and to the bandwidth conditions of the network. The real-time control is based on a collection of adjustable parameters relating both to aspects of implementation and to the hardware with which the algorithm is processed. The proposed encoding system is evaluated in terms of compression ratio, processing delay and quality of the compressed image when compared with the standard method

Design and Implementation of Hybrid Multiplier for DSP Applications

In recent decades, there has been a consistent reduction in feature sizes in integrated circuit (IC) technology, leading to the need for increased placement of functional circuits on each chip. When it comes to the design of digital circuits, there is a significant focus on hybrid logic. Hybrid logic is highly regarded due to its ability to consume less power while achieving higher efficiency. Hybrid logic circuits have similarities to complementary metal-oxide-semiconductor (CMOS) transistors, yet possess a reduced transistor count while offering enhanced performance and reliability capabilities. This study examines the modeling and implementation hybrid multiplier with of help of hybrid adder. The functionality of adder is determined with the help of hybrid logic producing XOR/XNOR functionalities in single circuit.    The proposed hybrid Multiplier, which incorporates a hybrid Adder, has been successfully designed and implemented using CMOS 45nm technology and Mentor Graphics software the hybrid transistor logic multiplier demonstrates a decrease in total delay of 60% compared to CMOS

Compressor based approximate multiplier architectures for media processing applications

Approximate computing is an attractive technique to gain substantial improvement in the area, speed, and power in applications where exact computation is not required. This paper proposes two improved multiplier designs based on a new 4:2 approximate compressor circuit to simplify the hardware at the partial product reduction stage. The proposed multiplier designs are targeted towards error-tolerant applications. Exhaustive error and hardware analysis has been carried out on the existing and proposed multiplier designs. The results prove that the proposed approximate multiplier architecture performs better than the existing architectures without significant compromise on quality metrics. Experimental results show that die-area and power consumed are reduced upto 28%, and 25.29% respectively in comparison with the existing designs without significant compromise on accuracy

A Study on Efficient Designs of Approximate Arithmetic Circuits

Approximate computing is a popular field where accuracy is traded with energy. It can benefit applications such as multimedia, mobile computing and machine learning which are inherently error resilient. Error introduced in these applications to a certain degree is beyond human perception. This flexibility can be exploited to design area, delay and power efficient architectures. However, care must be taken on how approximation compromises the correctness of results. This research work aims to provide approximate hardware architectures with error metrics and design metrics analyzed and their effects in image processing applications. Firstly, we study and propose unsigned array multipliers based on probability statistics and with approximate 4-2 compressors, full adders and half adders. This work deals with a new design approach for approximation of multipliers. The partial products of the multiplier are altered to introduce varying probability terms. Logic complexity of approximation is varied for the accumulation of altered partial products based on their probability. The proposed approximation is utilized in two variants of 16-bit multipliers. Synthesis results reveal that two proposed multipliers achieve power savings of 72% and 38% respectively compared to an exact multiplier. They have better precision when compared to existing approximate multipliers. Mean relative error distance (MRED) figures are as low as 7.6% and 0.02% for the proposed approximate multipliers, which are better than the previous state-of-the-art works. Performance of the proposed multipliers is evaluated with geometric mean filtering application, where one of the proposed models achieves the highest peak signal to noise ratio (PSNR). Second, approximation is proposed for signed Booth multiplication. Approximation is introduced in partial product generation and partial product accumulation circuits. In this work, three multipliers (ABM-M1, ABM-M2, and ABM-M3) are proposed in which the modified Booth algorithm is approximated. In all three designs, approximate Booth partial product generators are designed with different variations of approximation. The approximations are performed by reducing the logic complexity of the Booth partial product generator, and the accumulation of partial products is slightly modified to improve circuit performance. Compared to the exact Booth multiplier, ABM-M1 achieves up to 15% reduction in power consumption with an MRED value of 7.9 × 10-4. ABM-M2 has power savings of up to 60% with an MRED of 1.1 × 10-1. ABM-M3 has power savings of up to 50% with an MRED of 3.4 × 10-3. Compared to existing approximate Booth multipliers, the proposed multipliers ABM-M1 and ABM-M3 achieve up to a 41% reduction in power consumption while exhibiting very similar error metrics. Image multiplication and matrix multiplication are used as case studies to illustrate the high performance of the proposed approximate multipliers. Third, distributed arithmetic based sum of products units approximation is analyzed. Sum of products units are key elements in many digital signal processing applications. Three approximate sum of products models which are based on distributed arithmetic are proposed. They are designed for different levels of accuracy. First model of approximate sum of products achieves an improvement up to 64% on area and 70% on power, when compared to conventional unit. Other two models provide an improvement of 32% and 48% on area and 54% and 58% on power, respectively, with a reduced error rate compared to the first model. Third model achieves MRED and normalized mean error distance (NMED) as low as 0.05% and 0.009%. Performance of approximate units is evaluated with a noisy image smoothing application, where the proposed models are capable of achieving higher PSNR than existing state of the art techniques. Fourth, approximation is applied in division architecture. Two approximation models are proposed for restoring divider. In the first design, approximation is performed at circuit level, where approximate divider cells are utilized in place of exact ones by simplifying the logic equations. In the second model, restoring divider is analyzed strategically and number of restoring divider cells are reduced by finding the portions of divisor and dividend with significant information. An approximation factor $p$ is used in both designs. In model 1, the design with p=8 has a 58% reduction in both area and power consumption compared to exact design, with a Q-MRED of 1.909 × 10-2 and Q-NMED of 0.449 × 10-2. The second model with an approximation factor p=4 has 54% area savings and 62% power savings compared to exact design. The proposed models are found to have better error metrics compared to existing designs, with better performance at similar error values. A change detection image processing application is used for real time assessment of proposed and existing approximate dividers and one of the models achieves a PSNR of 54.27 dB

High performance 8-bit approximate multiplier using novel 4:2 approximate compressors for fast image processing

In this paper, a novel 8-bit approximate multiplier is proposed based on three novel 4:2 approximate compressors which its delay and error is less than those of the multipliers constructed by traditional 4:2 approximate compressors, and its delay is also less than that of an 8-bit multiplier constructed by using 3:2 precise compressors. To do so, each novel compressor is designed such that its output carry is independent of the output carry of its previous compressor in the multiplier. Therefore, the problem of carry propagation delay is eliminated and a fast multiplier is constructed. To obtain the most accurate multiplier, the best compressor of the three proposed compressors for each multiplier’s column is determined using the genetic algorithm. Moreover, one can use the approximate compressors only at the k least significant multiplier’s columns for more error reduction. The proposed multiplier is used for image blending and image compression. Our simulations show that for example the error and the delay of the proposed method for k=9 is at-least 32.52% and 33.10% less than those of traditional 4:2 approximate compressor based multipliers, respectively.Abstract: In this paper, a novel 8-bit approximate multiplier is proposed based on three novel 4:2 approximate compressors which its delay and error is less than those of the multipliers constructed by traditional 4:2 approximate compressors, and its delay is also less than that of an 8-bit multiplier constructed by using 3:2 precise compressors. To do so, each novel compressor is designed such that its output carry is independent of the output carry of its previous compressor in the multiplier. Therefore, the problem of carry propagation delay is eliminated and a fast multiplier is constructed. To obtain the most accurate multiplier, the best compressor of the three proposed compressors for each multiplier’s column is determined using the genetic algorithm. Moreover, one can use the approximate compressors only at the k least significant multiplier’s columns for more error reduction. The proposed multiplier is used for image blending and image compression. Our simulations show that for example the error and the delay of the proposed method for k=9 is at-least 32.52% and 33.10% less than those of traditional 4:2 approximate compressor based multipliers, respectively

High Speed Low Area DA Based FIR Filter Using EGDI Adder

In this paper, we proposed a novel enhanced gate diffusion (EGDI) adder is designed and is implemented in Distributed Arithmetic (DA) based Finite Impulse Response (FIR) filter.  Generally, multipliers, adders, and shift accumulators are the basic blocks present in the FIR filters. The hardware architecture of multipliers is very high. To get rid of this multiplier less architecture is needed in the FIR filter. So Distributed Arithmetic architecture plays a key role in FIR filters which will occupy less area and increase the speed. To reduce the area further the adders in DA are designed using enhanced gate diffusion (EGDI) which increases the operation speed of the FIR filter and at the same time, the area will be decreased. The proposed design is synthesized and implemented in the Synapsis design compiler tool. The area, power delay product, frequency, area delay product, and power of the proposed design are calculated.  When we observe the proposed design has a 15% high-frequency rate when compared with the existing design. Also, the proposed design is more useful in signal, processing applications

High Speed Low Area DA Based FIR Filter Using EGDI Adder

In this paper, we proposed a novel enhanced gate diffusion (EGDI) adder is designed and is implemented in Distributed Arithmetic (DA) based Finite Impulse Response (FIR) filter.  Generally, multipliers, adders, and shift accumulators are the basic blocks present in the FIR filters. The hardware architecture of multipliers is very high. To get rid of this multiplier less architecture is needed in the FIR filter. So Distributed Arithmetic architecture plays a key role in FIR filters which will occupy less area and increase the speed. To reduce the area further the adders in DA are designed using enhanced gate diffusion (EGDI) which increases the operation speed of the FIR filter and at the same time, the area will be decreased. The proposed design is synthesized and implemented in the Synapsis design compiler tool. The area, power delay product, frequency, area delay product, and power of the proposed design are calculated.  When we observe the proposed design has a 15% high-frequency rate when compared with the existing design. Also, the proposed design is more useful in signal, processing applications