Lazy Model Expansion: Interleaving Grounding with Search

Finding satisfying assignments for the variables involved in a set of constraints can be cast as a (bounded) model generation problem: search for (bounded) models of a theory in some logic. The state-of-the-art approach for bounded model generation for rich knowledge representation languages, like ASP, FO(.) and Zinc, is ground-and-solve: reduce the theory to a ground or propositional one and apply a search algorithm to the resulting theory. An important bottleneck is the blowup of the size of the theory caused by the reduction phase. Lazily grounding the theory during search is a way to overcome this bottleneck. We present a theoretical framework and an implementation in the context of the FO(.) knowledge representation language. Instead of grounding all parts of a theory, justifications are derived for some parts of it. Given a partial assignment for the grounded part of the theory and valid justifications for the formulas of the non-grounded part, the justifications provide a recipe to construct a complete assignment that satisfies the non-grounded part. When a justification for a particular formula becomes invalid during search, a new one is derived; if that fails, the formula is split in a part to be grounded and a part that can be justified. The theoretical framework captures existing approaches for tackling the grounding bottleneck such as lazy clause generation and grounding-on-the-fly, and presents a generalization of the 2-watched literal scheme. We present an algorithm for lazy model expansion and integrate it in a model generator for FO(ID), a language extending first-order logic with inductive definitions. The algorithm is implemented as part of the state-of-the-art FO(ID) Knowledge-Base System IDP. Experimental results illustrate the power and generality of the approach

Introduction to IND and recursive partitioning, version 1.0

This manual describes the IND package for learning tree classifiers from data. The package is an integrated C and C shell re-implementation of tree learning routines such as CART, C4, and various MDL and Bayesian variations. The package includes routines for experiment control, interactive operation, and analysis of tree building. The manual introduces the system and its many options, gives a basic review of tree learning, contains a guide to the literature and a glossary, lists the manual pages for the routines, and instructions on installation

Introduction in IND and recursive partitioning

This manual describes the IND package for learning tree classifiers from data. The package is an integrated C and C shell re-implementation of tree learning routines such as CART, C4, and various MDL and Bayesian variations. The package includes routines for experiment control, interactive operation, and analysis of tree building. The manual introduces the system and its many options, gives a basic review of tree learning, contains a guide to the literature and a glossary, and lists the manual pages for the routines and instructions on installation

Design of Quaternary Logic Carry Look-Ahead Adder

In today's state-of-the-art VLSI technology, binary number system has been the choice for designing digital subsystems. Although technology development has made down scaling of devices possible, which in turn has resulted in a remarkable increase in density and functionality of VLSI systems, there are also significant drawbacks associated to the conventional binary number based system implementations. As the number of devices in VLSI circuits increases to billion of transistors in a chip area of , interconnection between the active devices both on chip and outside of a chip becomes considerably complicated. In a typical VLSI chip, about 70 percent of the chip area is occupied by interconnections whereas just 10 percent of the chip area is devoted to the devices and the remaining 20 percent is used for insulation. mm2 In this situation, multiple valued logics have attracted a considerable attention of researchers as a solution to overcome the above mentioned problem. Since fewer digits are required to represent a number in higher radices than in the binary number system, multiple valued logic circuits have the potential to minimize the number of interconnections. This thesis presents voltage-mode quaternary (4-valued) logic carry lookahead adder design using Silicon-On-Insulator (SOI) MOSFETs. The choice of adder subsystem is made because addition operation is the most frequently used operation in a general purpose system and in application specific processors. Further more, the other operations like subtraction, multiplication and division are based on addition operation of the arithmetic unit. In this study, an efficient logic to realize 4-valued logic addition operation is proposed. The presented method is in conjunction with binary logic concepts and is easily developed for look-ahead logic. Following the proposed method has resulted in logic circuits with shorter gate depth and faster speed of operation as compared to what the other researchers have proposed. To meet the design requirements of the proposed low-voltage low-power circuits, multiple threshold voltage SOI MOSFETs are used. This choice is made because of their capability to operate at low power supply voltages and their ability to remain at the adjusted threshold voltages while presenting better subthreshold characteristics compared to the bulk MOSFETs. The proposed half and full adder blocks are divided into a few subblocks which could be considered as primitive gates. Transistor-Resistor Logic is used to implement each of them. Spice simulations have been performed on the proposed logic subblocks and their transient behaviors have been studied. Finally, the propagation delay, power consumption and overall performance of the proposed circuits are compared with other adder circuits proposed by other researchers. The presented adder circuits in this work have shown up to 58% reduction in critical propagation delay and 20% less power dissipation resulting in 64% reduction in power-delay product in comparison with other reported work. When compared to the binary logic carry look-ahead adder using the same technology (SOI), 54.39% improvement in power dissipation was achieved

Fast Heuristic and Exact Algorithms for Two-Level Hazard-Free Logic Minimization

None of the available minimizers for 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and automated circuit partitioning techniques. This paper introduces two new 2-level logic minimizers:ESPRESSO-HF, a heuristic method which is loosely based on ESPRESSO-II, and IMPYMIN, an exact method based on implicit data structures. Both minimizers can solve all currently available examples, which range up to 32 inputs and 33 outputs.These include examples that have never been solved before.For examples that can be solved by other minimizers our methods are several orders of magnitude faster. As by-products of these algorithms, we also present two additional results. First, we introduce a fast new algorithm to check if a hazard-free covering problem can feasibly be solved. Second, we introduce a novel formulation of the 2-level hazard-free logic minimization problem by capturing hazard-freedom constraints within a synchronous function by adding new variables