Generic radiation hardened photodiode layouts for deep submicron CMOS image sensor processes

Selected radiation hardened photodiode layouts, manufactured in a deep submicron CMOS Image Sensor technology, are irradiated by 60Co gamma-rays up to 2.2 Mrad(SiO2) and studied in order to identify the most efficient structures and the guidelines (recess distance, bias voltage) to follow to make them work efficiently in such technology. To do so, both photodiode arrays and active pixel sensors are used. After 2.2 Mrad(SiO2), the studied sensors are fully functional and most of the radiation hardened photodiodes exhibit radiation induced dark current values more than one order of magnitude lower than the standard photodiode

Silicon carbide semiconductor device fabrication and characterization

A number of basic building blocks i.e., rectifying and ohmic contacts, implanted junctions, MOS capacitors, pnpn diodes and devices, such as, MESFETs on both alpha and beta SiC films were fabricated and characterized. Gold forms a rectifying contact on beta SiC. Since Au contacts degrade at high temperatures, these are not considered to be suitable for high temperature device applications. However, it was possible to utilize Au contact diodes for electrically characterizing SiC films. Preliminary work indicates that sputtered Pt or Pt/Si contacts on beta SiC films are someways superior to Au contacts. Sputtered Pt layers on alpha SiC films form excellent rectifying contacts, whereas Ni layers following anneal at approximately 1050 C provide an ohmic contact. It has demonstrated that ion implantation of Al in substrates held at 550 C can be successfully employed for the fabrication of rectifying junction diodes. Feasibility of fabricating pnpn diodes and platinum gated MESFETs on alpha SiC films was also demonstrated

Charge-based silicon quantum computer architectures using controlled single-ion implantation

We report a nanofabrication, control and measurement scheme for charge-based silicon quantum computing which utilises a new technique of controlled single ion implantation. Each qubit consists of two phosphorus dopant atoms ~50 nm apart, one of which is singly ionized. The lowest two energy states of the remaining electron form the logical states. Surface electrodes control the qubit using voltage pulses and dual single electron transistors operating near the quantum limit provide fast readout with spurious signal rejection. A low energy (keV) ion beam is used to implant the phosphorus atoms in high-purity Si. Single atom control during the implantation is achieved by monitoring on-chip detector electrodes, integrated within the device structure, while positional accuracy is provided by a nanomachined resist mask. We describe a construction process for implanted single atom and atom cluster devices with all components registered to better than 20 nm, together with electrical characterisation of the readout circuitry. We also discuss universal one- and two-qubit gate operations for this architecture, providing a possible path towards quantum computing in silicon.Comment: 9 pages, 5 figure

Study of the effects of deuterium implantation upon the performance of thin-oxide CMOS devices

The use of ultra thin oxide films in modem semiconductor devices makes them increasingly susceptible to damage due to the hot carrier damage. Deuterium in place of hydrogen was introduced by ion implantation at the silicon oxide-silicon interface during fabrication to satisfy the dangling bonds. Deuterium was implanted at energies of 15, 25 and 35 keV and at a dose of 1x1014/cm2. Some of the wafers were subjected to N2O annealing following gate oxide growth. It was demonstrated that ion implantation is an effective means of introduction of deuterium. Deuterium implantation brings about a clear enhancement in gate oxide quality by improving the interface characteristics. N2O annealing further improves device performance. A reduction of electron traps with deutenum was also observed. A combination of deuterium implantation at 25 keV and a dose of 1x1015/cm2, followed by annealing in N2O was observed to have the most positive influence on device behavior. Concurrently, MEMS microheaters being fabricated for an integrated VOC sensor were also tested for their temperature response to an applied voltage. Different channel configurations and materials for the conducting film were compared and the best pattern for rapid heating was identified. Temperature rises of upto 390° C were obtained. The temperature responses after coating spin-on glass in the microchannels were also measured