CAD methodologies for low power and reliable 3D ICs

The main objective of this dissertation is to explore and develop computer-aided-design (CAD) methodologies and optimization techniques for reliability, timing performance, and power consumption of through-silicon-via(TSV)-based and monolithic 3D IC designs. The 3D IC technology is a promising answer to the device scaling and interconnect problems that industry faces today. Yet, since multiple dies are stacked vertically in 3D ICs, new problems arise such as thermal, power delivery, and so on. New physical design methodologies and optimization techniques should be developed to address the problems and exploit the design freedom in 3D ICs. Towards the objective, this dissertation includes four research projects. The first project is on the co-optimization of traditional design metrics and reliability metrics for 3D ICs. It is well known that heat removal and power delivery are two major reliability concerns in 3D ICs. To alleviate thermal problem, two possible solutions have been proposed: thermal-through-silicon-vias (T-TSVs) and micro-fluidic-channel (MFC) based cooling. For power delivery, a complex power distribution network is required to deliver currents reliably to all parts of the 3D IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. In this project, a co-optimization methodology for signal, power, and thermal interconnects in 3D ICs is presented. The goal of the proposed approach is to improve signal, thermal, and power noise metrics and to provide fast and accurate design space explorations for early design stages. The second project is a study on 3D IC partition. For a 3D IC, the target circuit needs to be partitioned into multiple parts then mapped onto the dies. The partition style impacts design quality such as footprint, wirelength, timing, and so on. In this project, the design methodologies of 3D ICs with different partition styles are demonstrated. For the LEON3 multi-core microprocessor, three partitioning styles are compared: core-level, block-level, and gate-level. The design methodologies for such partitioning styles and their implications on the physical layout are discussed. Then, to perform timing optimizations for 3D ICs, two timing constraint generation methods are demonstrated that lead to different design quality. The third project is on the buffer insertion for timing optimization of 3D ICs. For high performance 3D ICs, it is crucial to perform thorough timing optimizations. Among timing optimization techniques, buffer insertion is known to be the most effective way. The TSVs have a large parasitic capacitance that increases the signal slew and the delay on the downstream. In this project, a slew-aware buffer insertion algorithm is developed that handles full 3D nets and considers TSV parasitics and slew effects on delay. Compared with the well-known van Ginneken algorithm and a commercial tool, the proposed algorithm finds buffering solutions with lower delay values and acceptable runtime overhead. The last project is on the ultra-high-density logic designs for monolithic 3D ICs. The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high-density device integration at the individual transistor-level. The benefits and challenges of monolithic 3D integration technology for logic designs are investigated. First, a 3D standard cell library for transistor-level monolithic 3D ICs is built and their timing and power behavior are characterized. Then, various interconnect options for monolithic 3D ICs that improve design quality are explored. Next, timing-closed, full-chip GDSII layouts are built and iso-performance power comparisons with 2D IC designs are performed. Important design metrics such as area, wirelength, timing, and power consumption are compared among transistor-level monolithic 3D, gate-level monolithic 3D, TSV-based 3D, and traditional 2D designs.PhDCommittee Chair: Lim, Sung Kyu; Committee Member: Bakir, Muhannad; Committee Member: Kim, Hyesoon; Committee Member: Lee, Hsien-Hsin; Committee Member: Mukhopadhyay, Saiba

Through-silicon-via-aware prediction and physical design for multi-granularity 3D integrated circuits

The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs. The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength. The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance. The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness. The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated. The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs.PhDCommittee Chair: Lim, Sung Kyu; Committee Member: Bakir, Muhannad; Committee Member: Kim, Hyesoon; Committee Member: Lee, Hsien-Hsin Sean; Committee Member: Mukhopadhyay, Saiba

Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

Working for the photolithography tool manufacturer leader sometimes gives me the impression of how complex and specific is the sector I am working on. This master thesis topic came with the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a helicopter view usually helps to understand where a process is in the productive chain, or what other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico

On-chip electrochemical capacitors and piezoelectric energy harvesters for self-powering sensor nodes

On-chip sensing and communications in the Internet of things platform have benefited from the miniaturization of faster and low power complementary-metal-oxide semiconductor (CMOS) microelectronics. Micro-electromechanical systems technology (MEMS) and development of novel nanomaterials have further improved the performance of sensors and transducers while also demonstrating reduction in size and power consumption. Integration of such technologies can enable miniaturized nodes to be deployed to construct wireless sensor networks for autonomous data acquisition. Their longevity, however, is determined by the lifetime of the power supply. Traditional batteries cannot fully fulfill the demands of sensor nodes that require long operational duration. Thus, we require solutions that produce their own electricity from the surroundings and store them for future utility. Furthermore, manufacturing of such a power supply must be compatible with CMOS and MEMS technology. In this thesis, we will describe on-chip electrochemical capacitors and piezoelectric energy harvesters as components of such a self-powered sensor node. Our piezoelectric microcantilevers confirm the feasibility of fabricating micro electro-mechanical-systems (MEMS) size two-degree-of-freedom systems which can address the major issue of small bandwidth of piezoelectric micro-energy harvesters. These devices use a cut-out trapezoidal cantilever beam, limited by its footprint area i.e. a 1 cm$^2$ silicon die, to enhance the stress on the cantilever\u27s free end while reducing the gap remarkably between its first two eigenfrequencies in the 400 - 500 Hz and in the 1 - 2 kHz range. The energy from the M-shaped harvesters could be stored in rGO based on-chip electrochemical capacitors. The electrochemical capacitors are manufactured through CMOS compatible, reproducible, and reliable micromachining processes such as chemical vapor deposition of carbon nanofibers (CNF) and spin coating of graphene oxide based (GO) solutions. The impact of electrode geometry and electrode thickness is studied for CNF based electrodes. Furthermore, we have also demonstrated an improvement in their electrochemical performance and yield of spin coated electrochemical capacitors through surface roughening from iron and chromium nanoparticles. The CVD grown CNF and spin coated rGO based devices are evaluated for their respective trade-offs. Finally, to improve the energy density and demonstrate the versatility of the spin coating process, we manufactured electrochemical capacitors from various GO based composites with functional groups heptadecan-9-amine and octadecanamine. The materials were used as a stack to demonstrate high energy density for spin coated electrochemical capacitors. We have also examined the possibility of integrating these devices into a power management unit to fully realize a self-powering on-chip power supply through survey of package fabrication, choice of electrolyte, and device assembly

Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

Fundamental Characterization of Low Dimensional Carbon Nanomaterials for 3D Electronics Packaging

Transistor miniaturization has over the last half century paved the way for higher value electronics every year along an exponential pace known as \u27Moore\u27s law\u27. Now, as the industry is reaching transistor features that no longer makes economic sense, this way of developing integrated circuits (ICs) is coming to its definitive end. As a solution to this problem, the industry is moving toward higher hanging fruits that can enable larger sets of functionalities and ensuring a sustained performance increase to continue delivering more cost-effective ICs every product cycle. These design strategies beyond Moore\u27s law put emphasis on 3D stacking and heterogeneous integration, which if implemented correctly, will deliver a continued development of ICs for a foreseeable future. However, this way of building semiconductor systems does bring new issues to the table as this generation of devices will place additional demands on materials to be successful. The international roadmap of devices and systems (IRDS) highlights the need for improved materials to remove bottlenecks in contemporary as well as future systems in terms of thermal dissipation and interconnect performance. For this very purpose, low dimensional carbon nanomaterials such as graphene and carbon nanotubes (CNTs) are suggested as potential candidates due to their superior thermal, electrical and mechanical properties. Therefore, a successful implementation of these materials will ensure a continued performance to cost development of IC devices.This thesis presents a research study on some fundamental materials growth and reliability aspects of low dimensional carbon based thermal interface materials (TIMs) and interconnects for electronics packaging applications. Novel TIMs and interconnects based on CNT arrays and graphene are fabricated and investigated for their thermal resistance contributions as well electrical performance. The materials are studied and optimized with the support of chemical and structural characterization. Furthermore, a reliability study was performed which found delamination issues in CNT array TIMs due to high strains from thermal expansion mismatches. This study concludes that CNT length is an important factor when designing CNT based systems and the results show that by further interface engineering, reliability can be substantially improved with maintained thermal dissipation and electrical performance. Additionally, a heat treatment study was made that enables improvement of the bulk crystallinity of the materials which will enable even better performance in future applications

Skybridge: A New Nanoscale 3-D Computing Framework for Future Integrated Circuits

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, continuing the traditional way of scaling to sub-20nm technologies is proving to be very difficult as MOSFETs are reaching their fundamental performance limits [1] and interconnection bottleneck is dominating IC operational power and performance [2]. Migrating to 3-D, as a way to advance scaling, has been elusive due to inherent customization and manufacturing requirements in CMOS architecture that are incompatible with 3-D organization. Partial attempts with die-die [3] and layer-layer [4] stacking have their own limitations [5]. We propose a new 3-D IC fabric technology, Skybridge [6], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge’s core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance/watt benefits, and 10x reduction in interconnect lengths vs. scaled 16-nm CMOS [6]. Fabric-level heat extraction features are found to be effective in managing IC thermal profiles in 3-D. This 3-D integrated fabric proposal overcomes the current impasse of CMOS in a manner that can be immediately adopted, and offers unique solution to continue technology scaling in the 21st century

Challenges and solutions for large-scale integration of emerging technologies

Title from PDF of title page viewed June 15, 2021Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (pages 67-88)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021The semiconductor revolution so far has been primarily driven by the ability to shrink devices and interconnects proportionally (Moore's law) while achieving incremental benefits. In sub-10nm nodes, device scaling reaches its fundamental limits, and the interconnect bottleneck is dominating power and performance. As the traditional way of CMOS scaling comes to an end, it is essential to find an alternative to continue this progress. However, an alternative technology for general-purpose computing remains elusive; currently pursued research directions face adoption challenges in all aspects from materials, devices to architecture, thermal management, integration, and manufacturing. Crosstalk Computing, a novel emerging computing technique, addresses some of the challenges and proposes a new paradigm for circuit design, scaling, and security. However, like other emerging technologies, Crosstalk Computing also faces challenges like designing large-scale circuits using existing CAD tools, scalability, evaluation and benchmarking of large-scale designs, experimentation through commercial foundry processes to compete/co-exist with CMOS for digital logic implementations. This dissertation addresses these issues by providing a methodology for circuit synthesis customizing the existing EDA tool flow, evaluating and benchmarking against state-of-the-art CMOS for large-scale circuits designed at 7nm from MCNC benchmark suits. This research also presents a study on Crosstalk technology's scalability aspects and shows how the circuits' properties evolve from 180nm to 7nm technology nodes. Some significant results are for primitive Crosstalk gate, designed in 180nm, 65nm, 32nm, and 7nm technology nodes, the average reduction in power is 42.5%, and an average improvement in performance is 34.5% comparing to CMOS for all mentioned nodes. For benchmarking large-scale circuits designed at 7nm, there are 48%, 57%, and 10% improvements against CMOS designs in terms of density, power, and performance, respectively. An experimental demonstration of a proof-of-concept prototype chip for Crosstalk Computing at TSMC 65nm technology is also presented in this dissertation, showing the Crosstalk gates can be realized using the existing manufacturing process. Additionally, the dissertation also provides a fine-grained thermal management approach for emerging technologies like transistor-level 3-D integration (Monolithic 3-D, Skybridge, SN3D), which holds the most promise beyond 2-D CMOS technology. However, such 3-D architectures within small form factors increase hotspots and demand careful consideration of thermal management at all integration levels. This research proposes a new direction for fine-grained thermal management approach for transistor-level 3-D integrated circuits through the insertion of architected heat extraction features that can be part of circuit design, and an integrated methodology for thermal evaluation of 3-D circuits combining different simulation outcomes at advanced nodes, which can be integrated to traditional CAD flow. The results show that the proposed heat extraction features effectively reduce the temperature from a heated location. Thus, the dissertation provides a new perspective to overcome the challenges faced by emerging technologies where the device, circuit, connectivity, heat management, and manufacturing are addressed in an integrated manner.Introduction and motivation -- Cross talk computing overview -- Logic simplification approach for Crosstalk circuit design -- Crostalk computing scalability study: from 180 nm to 7 nm -- Designing large*scale circuits in Crosstalk at 7 nm -- Comparison and benchmarking -- Experimental demonstration of Crosstalk computing -- Thermal management challenges and mitigation techniques for transistor-level- 3D integratio

A Digital Manufacturing Process For Three-Dimensional Electronics

Additive manufacturing (AM) offers the ability to produce devices with a degree of three-dimensional complexity and mass customisation previously unachievable with subtractive and formative approaches. These benefits have not transitioned into the production of commercial electronics that still rely on planar, template-driven manufacturing, which prevents them from being tailored to the end user or exploiting conformal circuitry for miniaturisation. Research into the AM fabrication of 3D electronics has been demonstrated; however, because of material restrictions, the durability and electrical conductivity of such devices was often limited. This thesis presents a novel manufacturing approach that hybridises the AM of polyetherimide (PEI) with chemical modification and selective light-based synthesis of silver nanoparticles to produce 3D electronic systems. The resulting nanoparticles act as a seed site for the electroless deposition of copper. The use of high-performance materials for both the conductive and dielectric elements created devices with the performance required for real-world applications. For printing PEI, a low-cost fused filament fabrication (FFF); also known as fused deposition modelling (FDM), printer with a unique inverted design was developed. The orientation of the printer traps hot air within a heated build environment that is open on its underside allowing the print head to deposit the polymer while keeping the sensitive components outside. The maximum achievable temperature was 120 °C and was found to reduce the degree of warping and the ultimate tensile strength of printed parts. The dimensional accuracy was, on average, within 0.05 mm of a benchmark printer and fine control over the layer thickness led to the discovery of flexible substrates that can be directly integrated into rigid parts. Chemical modification of the printed PEI was used to embed ionic silver into the polymer chain, sensitising it to patterning with a 405 nm laser. The rig used for patterning was a re-purposed vat-photopolymerisation printer that uses a galvanometer to guide the beam that is focused to a spot size of 155 µm at the focal plane. The positioning of the laser spot was controlled with an open-sourced version of the printers slicing software. The optimal laser patterning parameters were experimentally validated and a link between area-related energy density and the quality of the copper deposition was found. In tests where samples were exposed to more than 2.55 J/cm^2, degradation of the polymer was experienced which produced blistering and delamination of the copper. Less than 2.34 J/cm^2 also had negative effect and resulted in incomplete coverage of the patterned area. The minimum feature resolution produced by the patterning setup was 301 µm; however, tests with a photomask demonstrated features an order of magnitude smaller. The non-contact approach was also used to produce conformal patterns over sloped and curved surfaces. Characterisation of the copper deposits found an average thickness of 559 nm and a conductivity of 3.81 × 107 S/m. Tape peel and bend fatigue testing showed that the copper was ductile and adhered well to the PEI, with flexible electronic samples demonstrating over 50,000 cycles at a minimum bend radius of 6.59 mm without failure. Additionally, the PEI and copper combination was shown to survive a solder reflow with peak temperatures of 249°C. Using a robotic pick and place system a test board was automatically populated with surface mount components as small as 0201 resistors which were affixed using high-temperature, Type-V Tin-Silver-Copper solder paste. Finally, to prove the process a range of functional demonstrators were built and evaluated. These included a functional timer circuit, inductive wireless power coils compatible with two existing standards, a cylindrical RF antenna capable of operating at several frequencies below 10 GHz, flexible positional sensors, and multi-mode shape memory alloy actuators