Thermo-mechanical stress measurement and analysis in three dimensional interconnect structures

Three-dimensional (3-D) integration is effective to overcome the wiring limit imposed on device density and performance with continued scaling. The application of TSV (Through-Silicon Via) is essential for 3D IC integration. TSVs are embedded into the silicon substrate to form vertical, electrical connections between stacked IC chips. However, due to the large CTE mismatch between Silicon and Copper, thermal stresses are induced by various thermal histories from the device processing, and they have caused serious concerns regarding the thermal-mechanical reliability. Firstly, a semi-analytic approach is introduced to understand stress distributions in TSV structures. This is followed by application of finite element analysis for more accurate prediction of stress behavior according to the real geometry of the sample. The conventional Raman method is used to measure the linear combination of in-plane stress components near silicon top surface Secondly, the limitation of conventional Raman method is discussed: only certain linear combination of in-plane stress, instead of separate value for each stress components, can be obtained. Two different kinds of innovative Raman measurements have been developed and employed to study the normal stress components separately. Both of them take advantages of different laser polarization profiles to resolve the normal stress components separately based on experimental data. The top-down Raman measurements utilize so called “high NA effect” to obtain additional information, and can resolve all 3 normal stress components. Independent bending beam experiments are used to validate the results from cross-section Raman measurement on the same sample. The correlation between top-down Raman measurement and cross-section Raman measurement are investigated as well. Lastly, as a typical example of 3D IC package, a stack-die memory package is presented. Finite element analysis combined with cross-section Raman measurement and high resolution moiré interferometry were employed to investigate the thermal-mechanical reliability and chip-package interaction of the stack-die memory structure.Physic

Advances in panel glass packaging of mems and sensors for low stress and near hermetic reliability

MEMS based sensing is gaining widespread adoption in consumer electronics as well as the next generation Internet of Things (IoT) market. Such applications serve as primary drivers towards miniaturization for increased component density, multi-chip integration, lower cost and better reliability. Traditional approaches like System-on-Chip (SoC) and System on Board (SoB) are not ideal to address these challenges and there is a need to find solutions at package level, through heterogeneous package integration (HPI). However, existing MEMS packaging techniques like laminate/ceramic substrate packaging and silicon wafer level packaging face challenges like standardization, heterogeneous package integration and form factor miniaturization. Besides, application specific packages take up the largest fraction of the total manufacturing cost. Therefore, advanced packaging of MEMS sensors for HPI plays a critical role in the short and long run towards the SOP vision. This dissertation demonstrates a low stress, reliable, near-hermetic ultra-thin glass cavity MEMS packages as a solution that combines the advantages of LTCC/laminate substrates and silicon wafer level packaging while also addressing their limitations. These glass based cavity packages can be scaled down to 2x smaller form factors (<500μm) and are fabricated out of large panel fabrication processes thereby addressing the cost and form factor requirements of MEMS packaging. Flexible cavity design, advances in through-glass via technologies and dimensional stability of thin glass also enable die stacking and 3D assembly for sensor-processor integration towards sensor fusion. The following building block technologies were explored: (a) reliable cavity formation in thin glass panels (b) low stress glass-glass bonding, and (c) high throughput, fully filled through-package-via metallization in glass. Three main technical challenges were overcome to realize the objectives: (a) glass cracking, side wall taper, side wall roughness and defects, (b) interfacial voids at glass-polymer-glass interface and (c) electrical opens and high frequency performance of copper paste filled through-package-vias in glass.M.S

Aerospace Ceramic Materials: Thermal, Environmental Barrier Coatings and SiC/SiC Ceramic Matrix Composites for Turbine Engine Applications

Ceramic materials play increasingly important roles in aerospace applications because ceramics have unique properties, including high temperature capability, high stiffness and strengths, excellent oxidation and corrosion resistance. Ceramic materials also generally have lower densities as compared to metallic materials, making them excellent candidates for light-weight hot-section components of aircraft turbine engines, rocket exhaust nozzles, and thermal protection systems for space vehicles when they are being used for high-temperature and ultra-high temperature ceramics applications. Ceramic matrix composites (CMCs), including non-oxide and oxide CMCs, are also recently being incorporated in gas turbine engines for high pressure and high temperature section components and exhaust nozzles. However, the complexity and variability of aerospace ceramic processing methods, compositions and microstructures, the relatively low fracture toughness of the ceramic materials, still remain the challenging factors for ceramic component design, validation, life prediction, and thus broader applications. This ceramic material section paper presents an overview of aerospace ceramic materials and their characteristics. A particular emphasis has been placed on high technology level (TRL) enabling ceramic systems, that is, turbine engine thermal and environmental barrier coating systems and non-oxide type SiC/SiC CMCs. The current status and future trend of thermal and environmental barrier coatings and SiC/SiC CMC development and applications are described

Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics

The fundamental motivation for this dissertation is to address the widening interconnect gap between integrated circuit (IC) demands and package substrates specifically for high frequency digital-RF systems applications. Moore's law for CMOS ICs predicts that transistor density on ICs will double approximately every 18 months. The current state-of-the-art in IC package substrates is at 20µm lines/spaces and 50-60µm microvia diameter using epoxy dielectrics with loss tangent above 0.01. The research targets are to overcome the barriers of current technologies and demonstrate a set of advanced materials and process technologies capable of 5-10µm lines and spaces, and 10-30µm diameter microvias in a multilayer 3-D wiring substrate using 10-25µm thin film dielectrics with loss tangent in the <0.005. The research elements are organized as follows with a clear focus on understanding and characterization of fundamental materials structure-processing-property relationships and interfaces to achieve the next generation targets. (a) Low CTE Core Substrate, (b) Low Loss Dielectrics with 25µm and smaller microvias, (c) Sub-10µm Width Cu Conductors, and (d) Integration of the various dielectric and conductor processes.Ph.D.Committee Chair: Tummala, Rao; Committee Member: Iyer, Mahadevan; Committee Member: Saxena, Ashok; Committee Member: Swaminathan, Madhavan; Committee Member: Wong, Chingpin

Gallium Nitride (GaN) specific mechanical phenomena and their influence on reliability in power HEMT operation

In den letzten Jahren ist Gallium Nitride (GaN) auf dem Markt für Leistungsbauelemente in größerem Maßstab angekommen, wodurch die Notwendigkeit eines tieferen Verständnisses der grundlegenden Interaktionen im Chip notwendig geworden ist. Umfangreiche Forschung wurde auf dem Gebiet der elektrischen Effekte durchgeführt, da dort die wichtigsten Unterschiede gegenüber Silicon (Si) liegen. Im Gegensatz zur generellen Forschungsrichtung fokussiert sich diese Arbeit auf neue mechanische und thermo-mechanische Phänomene, die bisher in Si Bauteilen nicht vorhanden waren. In Kapitel 3 wird die Wechselwirkung von mechanischer Spannung, Temperatur und elektrischem Feld besprochen. Die physikalischen Effekte, die diese Zustandsgrößen verbinden, werden im Detail erklärt und es wird gezeigt, welche Effekte aufgrund ihrer Größe sicher vernachlässigt werden können und welche einer näheren Untersuchung bedürfen. In Kapitel 4 werden die thermischen Fähigkeiten bei massiver thermischer Überlastung, die durch einen Kurschluss verursacht wird, diskutiert. Der Testaufbau, auf dem die Chips bis zum Ausfall gestresst werden, wird vorgestellt. Anschließend werden die ausgefallenen Bauelemente analysiert und die Grundursache mit Hilfe von der Finite Element Analysis (FEA) und einer umfassenden, detaillierten physikalischen Fehleranalyse erklärt. Zusätzliche Vorschläge für Verbesserungen in diesem speziellen Versagensmodus werden am Ende gegeben. Kapitel 5 gibt Einblicke in die Resonanzphänomene bei GaN. Da GaN piezoelektrisch ist kann es als Aktuator fungieren, um den gesamte Chip in Resonanz zu bringen. Dieses Phänomen ist vermessen worden und wird anschließend durch FEA simuliert. Die Simulation wird dann gegen die Messung validiert, um die Richtigkeit der Simulation sicherzustellen. Aus diesen Simulationen werden Schlussfolgerungen bezüglich der Zuverlässigkeit der beiden am meisten gefährdeten Schichten, der GaN Schicht und Chip Verbindungsschicht, gezogen. Zusätzlich werden am Ende Extremfälle diskutiert, die einen Ausblick auf kommende Chipgehäuse geben sollen.In recent years Gallium Nitride (GaN) has entered the market for power devices on a broader scale, increasing the need for a deeper understanding of fundamental interactions within such devices. Extensive research has been conducted in the field of electric effects since the main differences of GaN over Silicon (Si) lie there. In contrast to this, this thesis will focus on new mechanical and thermo-mechanical phenomena, previously not occurring in Si devices. Chapter 3 will introduce the interactions of the mechanical stress, the temperature and the electric field. The effects connecting these state variables are explained in detail and it will be shown which effects can be neglected and which ones need closer investigations. In Chapter 4 the thermal capabilities under massive thermal overload, caused by a short circuit pulse, are discussed. The setup, which is used to stress the chips until failure, is presented. Failed devices are analyzed extensively by in depth physical failure inspection methods. Root cause analysis is done by means of Finite Element Analysis (FEA) and in depth physical failure analysis, finally enabling to provide suggestions for improvements in this particular failure mode. Chapter 5 will elaborate on resonance phenomena in GaN. Since GaN is piezoelectric it can act as an actuator to resonate the whole chip assembly. This phenomenon is measured in two steps and subsequently investigated by FEA. The Finite Element (FE) simulation results are validated against the measurements to ensure the correctness of the FE model. From these simulations conclusions regarding the reliability of the two most failure prone layers, namely the GaN stack and the die attach layer, are drawn. Additionally extreme cases are discussed giving an outlook on this issue in advanced package assemblies

Micro-mechanisms of Surface Defects Induced on Aluminum Alloys during Plastic Deformation at Elevated Temperatures

Near-surface deformed layers developed on aluminum alloys significantly influence the corrosion and tribological behavior as well as reduce the surface quality of the rolled aluminum. The evolution of the near-surface microstructures induced on magnesium containing aluminum alloys during thermomechanical processing has been investigated with the aim generating an understanding of the influence of individual forming parameters on its evolution and examine the microstructure of the roll coating induced on the mating steel roll through material transfer during rolling. The micro-mechanisms related to the various features of near-surface microstructure developed during tribological conditions of the simulated hot rolling process were identified. Thermomechanical processing experiments were performed with the aid of hot rolling (operating temperature: 550 to 460 °C, 4, 10 and 20 rolling pass schedules) and hot forming (operating temperature: 350 to 545 °C, strain rate: 4 × 10-2 s-1) tribo-simulators. The surface, near-surface features and material transfer induced during the elevated temperature plastic deformation were examined and characterized employing optical interferometry, SEM/EDS, FIB and TEM. Near-surface features characterized on the rolled aluminum alloys included; cracks, fractured intermetallic particles, aluminum nano-particles, oxide decorated grain boundaries, rolled-in oxides, shingles and blisters. These features were related to various individual rolling parameters which included, the work roll roughness, which induced the formation of shingles, rolling marks and were responsible for the redistribution of surface oxide and the enhancements of the depth of the near-surface damage. The enhanced stresses and strains experienced during rolling were related to the formation and propagation of cracks, the nanocrystalline structure of the near-surface layers and aluminum nano-particles. The mechanism of the evolution of the near-surface microstructure were determined to include grain boundary sliding which induced the cracks at the surface and subsurface of the alloy, magnesium diffusion to free surfaces, crack propagation from shear stresses and the shear strains inducing the nanocrystalline grain structure, the formation of shingles by the shear deformation of micro-wedges induced by the work roll grooves, and the deformation of this oxide covered micro-wedges inducing the rolled-in oxides. Magnesium diffusion to free surfaces was identified as inducing crack healing due to the formation of MgO within cracks and was responsible for the oxide decorated grain boundaries. An examination of the roll coating revealed a complex layered microstructure that was induced through tribo-chemical and mechanical entrapment mechanisms. The microstructure of the roll coating suggested that the work roll material and the rolled aluminum alloy were essential in determining its composition and structure. Subsequent hot forming processes revealed the rich oxide-layer of the near-surface microstructure was beneficial for reducing the coefficient of friction during tribological contact with the steel die. Damage to the microstructure include cracks induced from grain boundary sliding of near-surface grains and the formation of oxide fibres within cracks of the near-surface deformed layers

The Development of Novel Interconnection Technologies for 3D Packaging of Wire Bondless Silicon Carbide Power Modules

This dissertation advances the cause for the 3D packaging and integration of silicon carbide power modules. 3D wire bondless approaches adopted for enhancing the performance of silicon power modules were surveyed, and their merits were assessed to serve as a vision for the future of SiC power packaging. Current efforts pursuing 3D wire bondless SiC power modules were investigated, and the concept for a novel SiC power module was discussed. This highly-integrated SiC power module was assessed for feasibility, with a focus on achieving ultralow parasitic inductances in the critical switching loops. This will enable higher switching frequencies, leading to a reduction in the size of the passive devices in the system and resulting in systems with lower weight and volume. The proposed concept yielded an order-of-magnitude reduction in system parasitics, alongside the possibility of a compact system integration. The technological barriers to realizing these concepts were identified, and solutions for novel interconnection schemes were proposed and evaluated. A novel sintered silver preform was developed to facilitate flip-chip interconnections for a bare-die power device while operating in a high ambient temperature. The preform was demonstrated to have 3.75× more bonding strength than a conventional sintered silver bond and passed rigorous thermal shock tests. A chip-scale and flip-chip capable power device was also developed. The novel package combined the ease of assembly of a discrete device with a performance exceeding a wire bonded module. It occupied a 14× smaller footprint than a discrete device, and offered power loop inductances which were less than a third of a conventional wire bonded module. A detailed manufacturing process flow and qualification is included in this dissertation. These novel devices were implemented in various electrical systems—a discrete Schottky barrier diode package, a half-bridge module with external gate drive, and finally a half-bridge with integrated gate driver in-module. The results of these investigations have been reported and their benefits assessed. The wire bondless modules showed \u3c 5% overshoot under all test conditions. No observable detrimental effects due to dv/dt were observed for any of the modules even under aggressive voltage slew rates of 20-25 V/ns

Experimental Characterization and Manufacture of Polymer Nanocomposite Dielectric Coatings for High-Temperature Superconductor Applications

Increased implementation of high-temperature superconducting (HTS) power transmission has the potential to revolutionize the efficiency of electrical grids and help unlock a fully electric transportation infrastructure. Realizing the benefits of HTS systems has been impeded by a lack of available dielectric insulation materials that can 1) withstand the extreme cryogenic operating environment of superconductors and 2) demonstrate low temperature processing that is compatible with existing superconductor manufacturing methods. Solving this problem necessitates a high-performance dielectric material with multifunctional properties specifically suited for operation in HTS systems. A polyamide and silicon dioxide (PA/SiO2) nanocomposite material with exceptional thermal stability has been developed as a solid dielectric coating solution. This study conducts mechanical, thermomechanical, and dielectric characterization efforts that explore multi-scale material property relationships in the nanocomposite to optimize it for this application. Additionally, an experimental manufacturing system is developed to provide a transition to large-scale processing of the nanocomposite coating material. The results of these efforts demonstrate a viable option to solve the material challenges impeding wider implementation of HTS power transmission and chart a path forward for the development of manufactured nanocomposite dielectrics