Investigation of high-K gate dielectrics for advanced CMOS application

Ph.DDOCTOR OF PHILOSOPH

Characterization and modeling of low-frequency noise in Hf-based high -kappa dielectrics for future cmos applications

The International Technology Roadmap for Semiconductors outlines the need for high-K dielectric based gate-oxide Metal Oxide Semiconductor Field Effect Transistors for sub-45 nm technology nodes. Gate oxides of hafnium seem to be the nearest and best alternative for silicon dioxide, when material, thermal and structural properties are considered. Usage of poly-Si as a gate electrode material degrades the performance of the device and hence gate stacks based on metal gate electrodes are gaining high interest. Though a substantial improvement in the performance has been achieved with these changes, reliability issues are a cause of concern. For analog and mixed-signal applications, low-frequency (I /f~ noise is a major reliability factor. Also in recent years. low frequency noise diagnostics has become a powerful tool for device performance and reliability characterization. This dissertation work demonstrates the necessity of gate stack engineering for achieving a low I/f noise performance. Changes in the material and process parameters of the devices, impact the 1/f noise behavior. The impact of 1/f noise on gate technology and processing parameters xvere identified and investigated. The thickness and the quality of the interfacial oxide, the nitridation effects of the layers, high-K oxide, bulk properties of the high-K layer. percentage of hafnium content in the high-K, post deposition anneal (PDA) treatments, effects of gate electrode material (poly-silicon. fully silicided or metal). Gate electrode processing are investigated in detail. The role of additional interfaces and bulk layers of the gate stack is understood. The dependence of low-frequency noise on high and low temperatures was also investigated. A systematic and a deeper understanding of these parameters on 1/f noise behavior are deduced which also forms the basis for improved physics-based 1/f noise modeling. The model considers the effect of the interfacial layer and also temperature, based on tunneling based thermally activated model. The simulation results of improved drain-current noise model agree well with the experimentally calculated values

FUNDAMENTAL ISSUE IN SPACE ELECTRONICS RELIABILITY: NEGATIVE BIAS TEMPERATURE INSTABILITY

Negative Bias Temperature Instability (NBTI) in silicon based metal-oxide-semiconductor-field-effect-transistors (MOSFETs) has been recognized as a critical reliability issue for advanced space qualified electronics. The phenomenon manifests itself as a modification of threshold voltage (Vth) resulting in degraded signal timing paths, and ultimately circuit failure. Despite the obvious importance of the issue, a standard measurement protocol has yet to be determined. This is a consequence of a large amount of complexity introduced by the strong dependencies of NBTI on temperature, electric field, frequency, duty cycle, and gate dielectric composition. We have improved upon the traditional measurement techniques which suffered from an underestimation of the magnitude of Vth shifts because they failed to account for trapped charge relaxation. Specifically, we have developed a means for measuring the maximum effect of NBTI by virtue of a method that can continuously monitor the Vth(t) without having to remove the stressing voltage. The interpretation methodology for this technique is explained in detail and the relevant approximations are justified. We have evidenced temperature and vertical electric field dependent Vth shifts in SiO2 and HfSiON devices. Furthermore, we have collected substantial evidence that the traditional \uf044Vth=At\uf061 analysis fails to explain the experimental data in the early time domain. Finally, we have discovered that \uf044Vth(t) on p-channel field effect transistors with HfSiON gate dielectrics is dependent upon the magnitude of Vds during the stressing cycle. To our knowledge this is not anticipated by any prior modeling attempts. We justify the exclusion of short channel effects as a possibility, leading us to conclude that positive charge in the dielectric stack is laterall

Characterization of high-k layers as the gate dielectric for MOSFETs

As the gate oxide thickness of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is continuously scaled down with lateral device dimensions, the gate leakage current during operation increases exponentially. This increase in leakage current raises concerns regarding power consumption and device reliability. Alternative dielectrics with higher dielectric constant (high-k) than that of Si02 have been searched. High-k layers allow the use of physically thicker gate dielectrics, so that the gate leakage current is controlled. The intensive world-wide research has identified the Hf-dielectric as the lead candidate for future CMOS technologies. However, the commercial application of Hf-dielectrics as the gate oxide has been held back by a number of issues, including process integration, low carrier mobility, and high instability. This project focuses on characterizing the defect responsible for the instability of Hf-dielectrics. The thesis consists of six chapters. After an introduction in Chapter 1, the characterization techniques used are described in Chapter 2. Two main contributions are: setting up the pulse transfer characteristic technique and developing a newly improved charge pumping technique called Variable T charged is charge Pumping (VT2CP). The research results are presented in Chapters 3,4 and 5. Chapter 3 characterizes a s-grown electron traps in HfO2/SiO2s tacks. The issues addressed include the impact of measurement technique on electron trapping, contribution of different current components to trapping, trap location, and the capture cross section and trapping kinetics. It is shown that the use of pulse transfer characteristic technique is essential for measuring electron trapping, since the traditional quasi-dc transfer characteristic is too IV ABSTRACT slow and the loss of charges is significant. The trap assisted tunneling and the thermally enhanced conduction contributes little to trapping. The trapping does not pile up at the interfaces and the region near to one or both ends of Hf02 has little trapping, when compared with the trapping in the bulk. To evaluate the electron fluency through the gate stack, efforts are made to estimate the trapping-induced transient gate current through simulation. This allows the determination of two capture cross sections: one in the order of 10-14cma2n d the other in the order of 10-16cm2. Chapter 4 concentrates on the characterization of generated electron traps and the time dependent dielectric breakdown (TDDB). Amplitude charge pumping and frequency sweep charge pumping are used to investigate the impact of gate electrodes and channel length on charging and discharging of the bulk defects. As channel length increases,it is found that bulk trapping increases and TDDB time shortens. Efforts are made to show that there is a quantitative correlation between the trapping and TDDB data. The newly improved VTZCP is used to separate trapping in the interfacial Si02 from that in Hf02. The results show that new traps are generated in both layers and the generation follows a power law with similar power factors. Investigation is also carried out to assess the dependence of trap generation on process and deposition conditions. Finally, it is found that Hf-dielectric with metal gate always suffers hard-breakdown. In Chapter 5, attention is turned to positive charging in Hf-dielectric. It is shown that the use of metal gate enhances the positive charging, when stressed under a positive gate bias. This is explained by assuming that there is a large number of hydrogenous species within the metal gate or at its interface with gate dielectric. Two types of threshold voltage instabilities have been identified for pMOSFETs. The first one results in a loop in the transfer characteristics when a pulse is applied to the gate. The second one is caused by the generation of new positive charge. Both are enhanced by V ABSTRACT nitridation. For sub-2nm Hf-dielectric, the threshold voltage instability of pMOSFETs can be more severe than that of nMOSFETs and it can be a limiting factor for the operation voltage. Finally, the project is summarized in Chapter 6 and the future work is discussed

Advanced gate stacks for nano-scale CMOS technology

Ph.DDOCTOR OF PHILOSOPH

Work function and process integration issues of metal gate materials in CMOS technology

Ph.DDOCTOR OF PHILOSOPH