Progress of nanopositioning and nanomeasuring machines for cross-scale measurement with sub-nanometre precision

Nanopositioning and nanomeasuring machines (NPM-machines), developed at Technische Universität Ilmenau, have provided high-precision measurement and positioning of objects across ten decades, from 20 pm resolution up to 200 mm measuring range. They work on the basis of the error-minimal, extended six degrees of freedom Abbe-comparator principle, with high-precision fibre-coupled laser interferometers and optical or atomic force probes. These machines are suitable not only for measuring but also for positioning with an outstanding sub-nanometre performance. Measurements on precision step heights up to 5 mm show a repeatability of 20 pm. Consecutive step positioning of 80 pm can be demonstrated. With the new approach of an atomic clock-stabilized He–Ne-laser via a high-stable-frequency comb, we achieve a frequency stability of less than 300 Hz, respectively 0.6 ċ 10−12 relative frequency stability within 1 h at an integration time of 1 s. For the first time, we can demonstrate a direct, permanent and unbroken chain of traceability between the laser interferometric measurement within an NPM-machine and a GPS satellite-based atomic clock. This paper presents a closer insight into the scientific and metrological background as well as unrivalled measurement results, and discusses the great possibilities of this new technology

Optimal Area Allocation for Yield Enhancement of DAC

Práce seznamuje s metodami návrhu pro zvýšení výtěžnosti a omezení chyb ve shodných strukturách. Systematické a náhodné chyby jsou shledány zdrojem neshod mezi strukturami. Je představen model náhodných chyb za využití log-normálové hustoty pravděpodobnosti. Pomocí nové metodologie založené na celočíselném pogramování (celočíselné optimalizaci) je navržena optimalizace parametrické výtěžnosti integrovaných obvodů. Je představen algoritmus generování optimální topologie. Topologie je demonstrována na R-2R D/A převodníku a výsledky jsou porovnány s jivým řešením.Recent research in yield enhancement techniques and mitigation of device mismatch is presented. Systematic and random mismatch is studied and identified as the cause of device mismatch. Model based on log-normal PDF is introduced. Optimization of IC parameter yield is suggested and conducted with help of a new methodology based on mathematical programming. An algorithm for the impact based area allocation of critical matched devices is shown as well as algorithms for common centroid layout of different sized devices. Newly developed algorithms are presented on binary weighted R-2R DAC as it is a common IC and comparison to other solutions is given

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

A Statistical View of Architecture Design

Computer architectures are becoming more and more complicated to meet the continuouslyincreasing demand on performance, security and sustainability from applications. Many factorsexist in the design and engineering space of various components and policies in the architectures,and it is not intuitive how these factors interact with each other and how they make impactson the architecture behaviors. Seeking for the best architectures for specific applicationsand requirements automatically is even more challenging. Meanwhile, the architecture designneed to deal with more and more non-determinism from lower level technologies. Emergingtechnologies exhibit statistical properties inherently, such as the wearout phenomenon inNEMs, PCM, ReRAM, etc. Due to the manufacturing and processing variations, there alsoexists variability among different devices or within the same device (e.g. different cells onthe same memory chip). Hence, to better understand and control the architecture behaviors,we introduce the statistical perspective of architecture design: by specifying the architecturaldesign goals and the desired statistical properties, we guide the architecture design with thesestatistical properties and exploit a series of techniques to achieve these properties.In the first part of the thesis, we introduce Herniated Hash Tables. Our architectural designgoal is that the hash table implementation is highly scalable in both storage efficiency andperformance, while the desired statistical property is to achieve as good storage efficiencyand performance as with uniform distributions given non-uniform distributions across hashbuckets. Herniated Hash Tables exploit multi-level phase change memory (PCM) to in-placeexpand storage for each hash bucket to accommodate asymmetrically chained entries. Theorganization, coupled with an addressing and prefetching scheme, also improves performancesignificantly by creating more memory parallelism.In the second part of the thesis, we introduce Lemonade from Lemons, harnessing devicewearout to create limited-use security architectures. The architectural design goal is tocreate hardware security architectures that resist attacks by statistically enforcing an upperbound on hardware uses, and consequently attacks. The desired statistical property is that thesystem-level minimum and maximum uses can be guaranteed with high probabilities despite ofdevice-level variability. We introduce techniques for architecturally controlling these boundsand explore the cost in area, energy and latency of using these techniques to achieve systemlevelusage targets given device-level wearout distributions.In the third part of the thesis, we demonstrate Memory Cocktail Therapy: A General,Learning-Based Framework to Optimize Dynamic Tradeoffs in NVMs. Limited write enduranceand long latencies remain the primary challenges of building practical memory systems fromNVMs. Researchers have proposed a variety of architectural techniques to achieve differenttradeoffs between lifetime, performance and energy efficiency; however, no individual techniquecan satisfy requirements for all applications and different objectives. Our architecturaldesign goal is that NVM systems can achieve optimal tradeoffs for specific applications andobjectives, and the statistical goal is that the selected NVM configuration is nearly optimal.Memory Cocktail Therapy uses machine learning techniques to model the architecture behaviorsin terms of all the configurable parameters based on a small number of sample configurations.Then, it selects the optimal configuration according to user-defined objectives whichleads to the desired tradeoff between performance, lifetime and energy efficiency

Transmissionselektronenmikroskopie an memristiven Bauteilen

The aim of the research unit Memristive Devices for Neuronal Systems is to develop, manufacture and understand microelectronic devices that can change their electrical resistance repeatedly and reversibly dependent on their history of operation, commonly called memristors. In the framework of this research unit this work was conducted and encompasses the complete procedure of micro- and nanostructural analysis starting with the sample preparation for transmission electron microscopy (TEM), the methods of analysis and concludes with the results and their interpretation. Besides conceptualization, fabrication and functional probing, the analysis described in this study is essential for understanding the mode of action and validation of expected results. Out of the various concepts for memristors, the most promising ones pursued within this research unit are a combined aluminum oxide tunnel barrier and a niobium oxide Schottky barrier – in short called double barrier device – and a bimetallic nanoparticle based electrochemical metallization cell (EMC) approach. Besides all-electronic memristors other approaches utilize non-linear sensor devices – e.g. gas or pressure sensors – to combine memristors and sensors into memsensors. The devices allow a sensor to "acclimatize" to baseline stimuli but still react to changes from this baseline input to report deviations. First concepts for these devices based on highly porous CdTe or InP microstructures have been investigated for the crystallinity and chemical impurities under different growth conditions. The investigations led to a deeper understanding of the fabrication process and the mechanisms of memristive switching ultimately enabling improvement of device design and fabrication.Das Ziel der Forschergruppe „Memristive Bauelemente für neuronale Systeme“ ist es, mikroelektronische Bauelemente zu entwickeln und produzieren, welche ihren elektrischen Widerstand wiederholt und reversibel ändern können; im Sprachgebrauch werden diese Bauelemente Memristoren genannt. Im Rahmen dieser Forschergruppe entstand diese Arbeit, welche das komplette Vorgehen der mikro- und nanostrutkurellen Analyse umreißt, von der Probenpräparation für das Transmissionelektronenmikroskop (TEM) über die analytischen Methoden bis hin zu den Ergebnisse und ihrer Interpretation. Neben der konzeptionellen Entwicklung, der Herstellung und der funktionellen Untersuchung der Memristoren sind die hier beschriebenen Forschungsergebnisse essentiell, um deren Wirkweise zu verstehen und die nach der Herstellung erwarteten Ergebnisse zu validieren. Von den vielen verschiedenen Konzepten, welche es für Memristoren gibt, stechen zwei als besonders vielversprechend hervor, welche in der Forschergruppe fokussiert untersucht wurden. Zum einen handelt es sich dabei um ein sogenanntes „Doppelbarrieren“-Bauelement, welches eine Aluminiumoxid-Tunnelbarriere mit einer Nioboxid-Schottkybarriere kombiniert, zum anderen ein auf bimetallischen Nanopartikeln basierte elektrochemische Metallisierungszelle. Neben den rein elektrischen Memristoren gibt es auch Ansätze, welche Sensoren und Memristoren miteinander zu verheiraten versuchen. Hierzu zählen zum Beispiel Gas- und Drucksensoren, welche sich an ein Grundniveau „gewöhnen“ können, und trotzdem auf Veränderungen von diesem Niveau anspringen. Erste Konzepte für diese Bauelemente bestehen aus hochporösen CdTe- oder InP-Mikrostrukturen und wurden auf ihre Kristallinität und Zusammensetzung unter verschiedenen Herstellungsbedingungen untersucht. Die Ergebnisse führten insgesamt zu einem tieferen Verständnis der Herstellungsprozesse und der zugrundeliegenden memristiven Schaltmechanismen. Ultimativ ebnet dies den Weg, sowohl Design als auch Herstellung der Bauelemente zu verbessern

Cross-Layer Pathfinding for Off-Chip Interconnects

Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects

Artificial Intelligence in Materials Science: Applications of Machine Learning to Extraction of Physically Meaningful Information from Atomic Resolution Microscopy Imaging

Materials science is the cornerstone for technological development of the modern world that has been largely shaped by the advances in fabrication of semiconductor materials and devices. However, the Moore’s Law is expected to stop by 2025 due to reaching the limits of traditional transistor scaling. However, the classical approach has shown to be unable to keep up with the needs of materials manufacturing, requiring more than 20 years to move a material from discovery to market. To adapt materials fabrication to the needs of the 21st century, it is necessary to develop methods for much faster processing of experimental data and connecting the results to theory, with feedback flow in both directions. However, state-of-the-art analysis remains selective and manual, prone to human error and unable to handle large quantities of data generated by modern equipment. Recent advances in scanning transmission electron and scanning tunneling microscopies have allowed imaging and manipulation of materials on the atomic level, and these capabilities require development of automated, robust, reproducible methods.Artificial intelligence and machine learning have dealt with similar issues in applications to image and speech recognition, autonomous vehicles, and other projects that are beginning to change the world around us. However, materials science faces significant challenges preventing direct application of the such models without taking physical constraints and domain expertise into account.Atomic resolution imaging can generate data that can lead to better understanding of materials and their properties through using artificial intelligence methods. Machine learning, in particular combinations of deep learning and probabilistic modeling, can learn to recognize physical features in imaging, making this process automated and speeding up characterization. By incorporating the knowledge from theory and simulations with such frameworks, it is possible to create the foundation for the automated atomic scale manufacturing

Novel electrical and chemical findings on SIOx-based ReRAM devices

Existing non-volatile flash memory technologies are characterised by slow access time, high power consumption and a quickly approaching scaling limit. Filamentary resistive RAM (ReRAM) is an emerging type of storage device that relies on the electrically driven change in resistance of a thin film sandwiched between two electrodes. The active region is often a binary oxide that develops a restorable conductive filament thanks to the electrically driven movement of oxygen. This technology offers potential sub-10 nm scalability, nanosecond programming with direct overwriting (unlike FLASH) and an appealing sub pJ/bit power consumption (compared to nJ/bit of FLASH). In this thesis, metal-insulator-metal ReRAM devices with a TiN/SiOx/TiN structure are used. While other binary oxides have been used in the literature, SiOx must be used in its amorphous form allowing for easier fabrication, and is an extremely well-studied material as its CMOS compatibility dates back 40 years. Using the above devices, it was possible to observe data storage performance comparable to the one of other types of ReRAM. More interestingly, it was observed that the resistance states of this family of devices may be programmed using nanosecond pulses of identical magnitude, possibly leading to simple programming circuits. Consequently, it is shown that this programming method may also be used to gradually increase or decrease the device resistance state as well as have devices enter states that relax over time. These types of behaviour mean that SiOx devices may be used in neuromorphic networks that require components whose behaviour resembles the one of the neuronal synapsis or the mammalian brain’s forgetting process. The literature reports on endurance-hindering electrode deformation phenomena during the operation of oxide-based ReRAM devices. A residual gas analyser (RGA) was used to detect that oxygen species are emitted during operation and therefore confirmed that such phenomena are caused by oxygen emission. Using SIMS (secondary ion mass spectroscopy) analysis on devices switched in atmospheres containing isotopically labelled oxygen, it was observed that, under deformed regions, it is possible to find incorporated atmospheric oxygen. Additionally, reducing atmospheric pressure had negative impact on device reliability. SiOx-based filamentary ReRAM is a strong candidate in the search for alternatives to flash memory. Moreover, these devices display behaviour that may be useful in applications trying to emulate the mammalian brain. Having observed device dependence on its atmosphere, endurance issues may now be addressed using electrodes capable of either adsorbing oxygen without bubbling or letting it go through without cracking

Reliability Characterisation of III-Nitrides Based Devices for Technology Development

III-nitrides based devices are considered as outstanding options for a range of extremely relevant applications. These devices can significantly improve the efficiency of high-power switching appliations. They are predicted to dominate applications in the low carbon economy. In recent years, these devices have been steadily improved and each year new record performances have been reported. Regardless of the superior performance of III-nitrides based devices, and particularly AlGaN/GaN high electron mobility transistors (HEMTs), achieving reliability at the same time as the high performance that the device boasts is a factor that is holding back widespread commercial and industrial development. Recoverable degradation (e.g. current collapse and on-resistance) and unrecoverable degradation (e.g. access resistance of contacts, and gate leakage current) persist to be limiting reliability factors. The mechanisms contributing towards performance and reliability degradation of AlGaN/GaN HEMTs, namely self-heating, charge trapping and strain, are required to be minimised; an important step before large-scale deployment can be attained. The strong coupling of these degradation mechanisms, under normal device operation, makes the quantitative contribution of each mechanism indistinct due to the lack of standard characterisation techniques. In this Thesis, the impact of the source/drain (S/D) and gate terminals of an AlGaN/GaN HEMT on its thermal management was investigated. Using Infrascope measurements, a substantial increase in temperature and resistance at the inner ends of the S/D contacts was observed. High-resolution X-ray diffraction technique combined with drift-diffusion (DD) simulations showed that strain reduction at the vicinity of S/D contacts is the origin of temperature rise. The strain reduction was also observed below the metal gate. Through electro-thermal simulations, the electrical stress on Ohmic contacts was shown to reduce the strain; leading to the inverse/converse piezoelectric effect. A new parametric technique was developed to decouple the mechanisms constituting device degradation in AlGaN/GaN HEMTs under normal device operation, namely self-heating and charge trapping. Both source (IS) and drain (ID) transient currents were used under various biasing conditions to analyse charge trapping behaviour. Two types of charge trapping mechanisms have been identified: (i) bulk trapping occurring on a time scale of 1 ms. Through monitoring the difference between I_S and I_D, bulk trapping time constant is shown to be independent of V_DS and V_GS. Also, V_GS is found to have no effect on the bulk trap density. Surface trapping is found to have a much greater impact on slow degradation when compared to self-heating and bulk trapping. At a short time scale (1ms), the dynamic ON resistance degradation is limited mainly by surface trapping accumulation and redistribution. Using the understanding of the degradation mechanism behaviour and origins, optimisations to the Ohmic and Schottky contacts as well as a new AlGaN/GaN HEMT architecture were proposed. In an attempt to improve the thermal management of S/D contacts, an Ohmic contact recess process is proposed to reduce the access resistance and enhance DC/RF performance of AlGaN/GaN HEMTs with a high Al concentration. A contact resistance (RC) of ~0.3 Ω.mm was achieved via optimal recess conditions. Small RC was found to lead to a higher current density at the inner edges of the contact, which resulted in a large increase of channel temperature beneath the S/D contacts. A highly n-doped AlGaN overgrowth layer was proposed to reduce the current density, and thus channel temperature at the Ohmic contacts. Titanium Nitride (TiN) Schottky processing was implemented to minimise the observed strain reduction beneath the gate metal. The optimal Schottky contact is obtained for TiN thicknesses of < 10 nm, which preserves the strain within the AlGaN barrier layer. As a result, Schottky barrier of 1.06 eV, a leakage current of 6 nA and improved linearity of 1.6 was achieved. In addition, C – V and I – V characterisations revealed very low trapping density within the optimised device. Lastly, a new device architecture was proposed to increase the 2-dimentional electron gas (2DEG) density and mobility, without compromising the enhancements of our proposed S/D and gate optimisations. This structure consists of (i) step-graded AlGaN barrier layer to increase strain and (ii) implementing AlN as the interfacial spacer layer