Low Noise and High Photodetection Probability SPAD in 180 nm Standard CMOS Technology

A square shaped, low noise and high photo-response single photon avalanche diode suitable for circuit integration, implemented in a standard CMOS 180 nm high voltage technology, is presented. In this work, a p+ to shallow n-well junction was engineered with a very smooth electric field profile guard ring to attain a photo detection probability peak higher than 50% with a median dark count rate lower than 2 Hz/μm2 when operated at an excess bias of 4 V. The reported timing jitter full width at half maximum is below 300 ps for 640 nm laser pulses

Temperature Characterization of a Fully-synthesizable Rail-to-Rail Dynamic Voltage Comparator operating down to 0.15-V

This paper deals with the performance/temperature tradeoff in an ultra-low voltage, ultra-low power rail-to-rail dynamic voltage comparator made solely by digital standard cells. The digital nature of the comparator makes its design technology portable also enabling its operation at very low supply voltages down to deep sub-threshold. In particular, as sub-threshold circuits have a significant temperature dependence, this paper focuses on the comparator performance under different supply voltages and temperatures.Measurements performed on a 180nm testchip show correct operation under rail-to-rail common-mode input at a supply voltage ranging from 0.6V down to 0.15V. Moreover, the measurements under temperature variations of offset, clock-to-output delay, and power in the range from -25 °C to 75 °C show the respective performance trade-offs

FPGA-Implemented Fractal Decoder with Forward Error Correction in Short-Reach Optical Interconnects

Forward error correction (FEC) codes combined with high-order modulator formats, i.e., coded modulation (CM), are essential in optical communication networks to achieve highly efficient and reliable communication. The task of providing additional error control in the design of CM systems with high-performance requirements remains urgent. As an additional control of CM systems, we propose to use indivisible error detection codes based on a positional number system. In this work, we evaluated the indivisible code using the average probability method (APM) for the binary symmetric channel (BSC), which has the simplicity, versatility and reliability of the estimate, which is close to reality. The APM allows for evaluation and compares indivisible codes according to parameters of correct transmission, and detectable and undetectable errors. Indivisible codes allow for the end-to-end (E2E) control of the transmission and processing of information in digital systems and design devices with a regular structure and high speed. This study researched a fractal decoder device for additional error control, implemented in field-programmable gate array (FPGA) software with FEC for short-reach optical interconnects with multilevel pulse amplitude (PAM-M) modulated with Gray code mapping. Indivisible codes with natural redundancy require far fewer hardware costs to develop and implement encoding and decoding devices with a sufficiently high error detection efficiency. We achieved a reduction in hardware costs for a fractal decoder by using the fractal property of the indivisible code from 10% to 30% for different n while receiving the reciprocal of the golden ratio

Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution Scaling

In this paper, a fully synthesizable digital-to-analog converter (DAC) is proposed. Based on a digital standard cell approach, the proposed DAC allows very low design effort, enables digital-like shrinkage across CMOS generations, low area at down-scaled technologies, and operation down to near-threshold voltages. The proposed DAC can operate at supply voltages that are significantly lower and/or at clock frequencies that are significantly greater than the intended design point, at the expense of moderate resolution degradation. In a 12-bit 40-nm testchip, graceful degradation of 0.3bit/100mV is achieved when V_DD is over-scaled down to 0.8V, and 1.4bit/100mV when further scaled down to 0.6V. The proposed DAC enables dynamic power-resolution tradeoff with 3X (2X) power saving for 1-bit resolution degradation at iso-sample rate (iso-resolution). A 12-bit DAC testchip designed with a fully automated standard cell flow in 40nm consumes 55µW at 27kS/s (9.1µW at 13.5kS/s) at a compact area of 500µm^2 and low voltage of 0.55V

A CMOS low pass filter for soc lock-in-based measurement devices

This paper presents a fully integrated Gm–C low pass ¿lter (LPF) based on a current ¿steering Gm reduction-tuning technique, specifically designed to operate as the output stage of a SoC lock-in amplifier. To validate this proposal, a first-order and a second-order single-ended topology were integrated into a 1.8 V to 0.18 µm CMOS (Complementary Metal-Oxide-Semiconductor) process, showing experimentally a tuneable cutoff frequency that spanned five orders of magnitude, from tens of mHz to kHz, with a constant current consumption (below 3 µA/pole), compact size (<0.0140 mm2 /pole), and a dynamic range better than 70 dB. Compared to state-of-the-art solutions, the proposed approach exhibited very competitive performances while simultaneously fully satisfying the demanding requirements of on-chip portable measurement systems in terms of highly efficient area and power. This is of special relevance, taking into account the current trend towards multichannel instruments to process sensor arrays, as the total area and power consumption will be proportional to the number of channels

A Human-Machine Interface Using Electrical Impedance Tomography for Hand Prosthesis Control

This paper presents a human-machine interface that establishes a link between the user and a hand prosthesis. It successfully uses electrical impedance tomography, a conventional bio-impedance imaging technique, using an array of electrodes contained in a wristband on the user's forearm. Using a high-performance analog front-end application specific integrated circuit (ASIC) the user's forearm inner bio-impedance redistribution is accurately assessed. These bio-signatures are strongly related to hand motions and using artificial neural networks, they can be learned so as to recognize the user's intention in real-time for prosthesis operation. In this work, eleven hand motions are designed for prosthesis operation with a gesture switching enabled sub-grouping method. Experiments with five subjects show that the system can achieve 98.5% accuracy with a grouping of three gestures and an accuracy of 94.4% with two sets of five gestures. The ASIC comprises a current driver with common-mode reduction capability and a current feedback instrumentation amplifier. The ASIC operates from $\pm$1.65 V power supplies, occupies an area of 0.07 mm2, and has a minimum bio-impedance sensitivity of 12.7 mΩp-p

Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS

In this paper, very compact, standard cell-based Digital-to-Analog converters (DACs) based on the Dyadic Digital Pulse Modulation (DDPM) are presented. As fundamental contribution, an optimal sampling condition is analytically derived to enhance DDPM conversion with inherent suppression of spurious harmonics. Operation under such optimal condition is experimentally demonstrated to assure resolution up to 16 bits, with 9.4–239X area reduction compared to prior art. The digital nature of the circuits also allows extremely low design effort in the order of 10 man-hours, portability across CMOS generations, and operation at the lowest supply voltage reported to date. The limitations of DDPM converters, the benefits of the optimal sampling condition and digital calibration were explored through the optimized design and the experimental characterization of two DACs with moderate and high resolution. The first is a general-purpose DAC for baseband signals achieving 12-bit (11.6 ENOB) resolution at 110kS/s sample rate and consuming $50.8\mu \text{W}$ , the second is a DAC for DC calibration achieving 16-bit resolution with 3.1-LSB INL, 2.5-LSB DNL, $45\mu \text{W}$ power, at only $530\mu \text{m}^{2}$ area

Конструкція автоматизованої системи протезу руки

В дипломному проекті розглянуто проблему відновлення втраченої або ампутованої кінцівки, шляхом проектування та розроблення протезу кінцівки, а саме руки з відновленням її косметичних та функціональних можливостей. Даний проект поділено на два розділи, один з них це конструкторський розділ, та технологічний розділ. Де конструкторський розділ це огляд літератури та патентів для вирішення заданих завдань та розробки даного проекту, конструкторський розділ, де відбувається побудова схем протезу, його систем руху, роботи і так далі. Проект розміщений на 84 сторінках, і містить 33 рисунків, 3 таблиці, 18 формул, 1 додаток, 71 літературних джерел. Наповнення конструкторського розділу це в першу чергу структура м’язового та рухового апарату людини, основи руху та методи ампутації верхніх кінцівок, для кращого розуміння схеми руху та функціоналу протезу. Наступні етапи це огляд побудов систем керування, та класифікація самих протезів, з оглядами патентів та інтелектуальної власності. Одним з важливих етапів буде аналіз сучасних пристроїв та після цього перехід до розробки загального вигляду конструкції автоматизованого протезу руки. Після чого вже ідуть етапи розробки електричних схем, систем руху, та повірки компонентів протезу. Наповненням технологічного розділу являється аналіз конструкції протезу з розрахунками технологічного процесу складання. Паралельно розробляються технологічний процес складання з розробками схем структурного складу та технологічного складання.The diploma project considered the problem of restoring a lost or amputated limb by designing and developing a limb prosthesis, namely a hand with the restoration of its cosmetic and functional capabilities. This project is divided into two sections, one of them is a design section and a technological section. Where the design section is a review of the literature and patents for solving the given tasks and the development of this project, the design section is where the construction of prosthesis schemes, its movement systems, work, and so on takes place. The project is placed on 83 pages and contains 33 figures, 3 tables, 18 formulas, 1 appendix, and 71 literary sources. The content of the design section is primarily the structure of the human muscular and motor apparatus, the basics of movement and methods of amputation of the upper limbs, for a better understanding of the movement scheme and functionality of the prosthesis. The next stages are a review of the construction of the control systems, and the classification of the prostheses themselves, with reviews of patents and intellectual property. One of the important stages will be the analysis of modern devices and, after that, the transition to the development of the general design of the automated hand prosthesis. After that, the stages of development of electrical circuits, motion systems, and verification of prosthesis components are already underway. The filling of the technological section is an analysis of the design of the prosthesis with calculations of the technological assembly process. In parallel, the technological assembly process is being developed with the development of schemes of structural composition and technological assembly

Advanced Memristor Modeling

The investigation of new memory schemes, neural networks, computer systems and many other improved electronic devices is very important for future generations of electronic circuits and for their widespread application in all the areas of industry. Relatedly, the analysis of new efficient and advanced electronic elements and circuits is an essential field of highly developed electrical and electronic engineering. The resistance-switching phenomenon, observed in many amorphous oxides, has been investigated since 1970 and is promising for inclusion in technologies for constructing new electronic memories. It has been established that such oxide materials have the ability to change their conductance in accordance to the applied voltage and memorizing their state for a long time interval. Similar behavior was predicted for the memristor element by Leon Chua in 1971. The memristor was proposed in accordance with symmetry considerations and the relationships between the four basic electric quantities—electric current i, voltage v, charge q and flux linkage Ψ. The memristor is a passive one-port element, together with the capacitor, inductor and resistor. The Williams Hewlett Packard (HP) research group has made a link between resistive switching devices and the memristor proposed by Chua. In addition, a number of scientific papers related to memristors and memristor devices have been issued and several models for them have been proposed. The memristor is a highly nonlinear component. It relates the electric charge q and the flux linkage Ψ, expressed as a time integral of the voltage v. It has the important capability of remembering the electric charge passing through its cross-section, and its respective resistance, when the electrical signals are switched off. Due to its nano-scale dimensions, non-volatility and memorizing properties, the memristor is a sound potential candidate for applications in high-density computer memories, artificial neural networks, and many other electronic devices