An approach to dynamic power consumption current testing of CMOS ICs

© 1995 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can be also detected. However, an important set of open and parametric defects escape quiescent power supply current testing because they prevent current elevation. Extending the consumption current testing time, from the static period to the dynamic one (i.e. considering the transient current), defects not covered with I/sub DDQ/ can be detected. Simulations using an on-chip sensor show that this technique can reach a high coverage for defects preventing current and also for those raising the static power consumption.Peer ReviewedPostprint (published version

Technology and layout-related testing of static random-access memories

Static random-access memories (SRAMs) exhibit faults that are electrical in nature. Functional and electrical testing are performed to diagnose faulty operation. These tests are usually designed from simple fault models that describe the chip interface behavior without a thorough analysis of the chip layout and technology. However, there are certain technology and layout-related defects that are internal to the chip and are mostly time-dependent in nature. The resulting failures may or may not seriously degrade the input/output interface behavior. They may show up as electrical faults (such as a slow access fault) and/or functional faults (such as a pattern sensitive fault). However, these faults cannot be described properly with the functional fault models because these models do not take timing into account. Also, electrical fault models that describe merely the input/output interface behavior are inadequate to characterize every possible defect in the basic SRAM cell. Examples of faults produced by these defects are: (a) static data loss, (b) abnormally high currents drawn from the power supply, etc. Generating tests for such faults often requires a thorough understanding and analysis of the circuit technology and layout. In this article, we shall examine ways to characterize and test such faults. We shall divide such faults into two categories depending on the types of SRAMs they effect—silicon SRAMs and GaAs SRAMs.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/43015/1/10836_2004_Article_BF00972519.pd

Behavior of faulty double BJT BiCMOS logic gates

Logic Behavior of a Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences

Open defects detection within 6T SRAM cells using a no write recovery test mode

Abstrac

An Experimental Evaluation of Resistive Defects and Different Testing Solutions in Low-Power Back-Biased SRAM Cells

This paper compares different types of resistive defects that may occur inside low-power SRAM cells, focusing on their impact on device operation. Notwithstanding the continuous evolution of SRAM device integration, manufacturing processes continue to be very sensitive to production faults, giving rise to defects that can be modeled as resistances, especially for devices designed to work in low-power modes. This work analyzes this type of resistive defect that may impair the device functionalities in subtle ways, depending on the defect characteristics and values that may not be directly or easily detectable by traditional test methods. We analyze each defect in terms of the possible effects inside the SRAM cell, its impact on power consumption, and provide guidelines for selecting the best test methods

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

Controllable polarity silicon nanowire transistors are among the promising candidates to replace current CMOS in the near future owing to their superior electrostatic characteristics and advanced functionalities. From a circuit testing point of view, it is unclear if the current CMOS and Fin-FET fault models are comprehensive enough to model all defects of controllable polarity nanowires. In this paper, we deal with the above problem using inductive fault analysis on three-independent-gate silicon nanowire FETs. Simulations revealed that the current fault models, i.e. stuck-open faults, are insufficient to cover all modes of operation. The newly introduced test algorithm for stuck open can adequately capture the malfunction behavior of controllable polarity logic gates in the presence of nanowire break and bridge on polarity terminals

Reliability-aware memory design using advanced reconfiguration mechanisms

Fast and Complex Data Memory systems has become a necessity in modern computational units in today's integrated circuits. These memory systems are integrated in form of large embedded memory for data manipulation and storage. This goal has been achieved by the aggressive scaling of transistor dimensions to few nanometer (nm) sizes, though; such a progress comes with a drawback, making it critical to obtain high yields of the chips. Process variability, due to manufacturing imperfections, along with temporal aging, mainly induced by higher electric fields and temperature, are two of the more significant threats that can no longer be ignored in nano-scale embedded memory circuits, and can have high impact on their robustness. Static Random Access Memory (SRAM) is one of the most used embedded memories; generally implemented with the smallest device dimensions and therefore its robustness can be highly important in nanometer domain design paradigm. Their reliable operation needs to be considered and achieved both in cell and also in architectural SRAM array design. Recently, and with the approach to near/below 10nm design generations, novel non-FET devices such as Memristors are attracting high attention as a possible candidate to replace the conventional memory technologies. In spite of their favorable characteristics such as being low power and highly scalable, they also suffer with reliability challenges, such as process variability and endurance degradation, which needs to be mitigated at device and architectural level. This thesis work tackles such problem of reliability concerns in memories by utilizing advanced reconfiguration techniques. In both SRAM arrays and Memristive crossbar memories novel reconfiguration strategies are considered and analyzed, which can extend the memory lifetime. These techniques include monitoring circuits to check the reliability status of the memory units, and architectural implementations in order to reconfigure the memory system to a more reliable configuration before a fail happens.Actualmente, el diseño de sistemas de memoria en circuitos integrados busca continuamente que sean más rápidos y complejos, lo cual se ha vuelto de gran necesidad para las unidades de computación modernas. Estos sistemas de memoria están integrados en forma de memoria embebida para una mejor manipulación de los datos y de su almacenamiento. Dicho objetivo ha sido conseguido gracias al agresivo escalado de las dimensiones del transistor, el cual está llegando a las dimensiones nanométricas. Ahora bien, tal progreso ha conllevado el inconveniente de una menor fiabilidad, dado que ha sido altamente difícil obtener elevados rendimientos de los chips. La variabilidad de proceso - debido a las imperfecciones de fabricación - junto con la degradación de los dispositivos - principalmente inducido por el elevado campo eléctrico y altas temperaturas - son dos de las más relevantes amenazas que no pueden ni deben ser ignoradas por más tiempo en los circuitos embebidos de memoria, echo que puede tener un elevado impacto en su robusteza final. Static Random Access Memory (SRAM) es una de las celdas de memoria más utilizadas en la actualidad. Generalmente, estas celdas son implementadas con las menores dimensiones de dispositivos, lo que conlleva que el estudio de su robusteza es de gran relevancia en el actual paradigma de diseño en el rango nanométrico. La fiabilidad de sus operaciones necesita ser considerada y conseguida tanto a nivel de celda de memoria como en el diseño de arquitecturas complejas basadas en celdas de memoria SRAM. Actualmente, con el diseño de sistemas basados en dispositivos de 10nm, dispositivos nuevos no-FET tales como los memristores están atrayendo una elevada atención como posibles candidatos para reemplazar las actuales tecnologías de memorias convencionales. A pesar de sus características favorables, tales como el bajo consumo como la alta escabilidad, ellos también padecen de relevantes retos de fiabilidad, como son la variabilidad de proceso y la degradación de la resistencia, la cual necesita ser mitigada tanto a nivel de dispositivo como a nivel arquitectural. Con todo esto, esta tesis doctoral afronta tales problemas de fiabilidad en memorias mediante la utilización de técnicas de reconfiguración avanzada. La consideración de nuevas estrategias de reconfiguración han resultado ser validas tanto para las memorias basadas en celdas SRAM como en `memristive crossbar¿, donde se ha observado una mejora significativa del tiempo de vida en ambos casos. Estas técnicas incluyen circuitos de monitorización para comprobar la fiabilidad de las unidades de memoria, y la implementación arquitectural con el objetivo de reconfigurar los sistemas de memoria hacia una configuración mucho más fiables antes de que el fallo suced

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design