RF system model for In-band full duplex communications

Abstract. In recent years by increasing the demands for communication services various technologies are examined in order to improve the throughput and spectrum efficiency of the wireless communication systems. For improving the performance a communication network, system deficiencies such as transmitter and receiver impairments need to be removed or compensated. One way to improve the network efficiency is to employ full duplex technology. Full duplex technology doubles the network capacity compared to the case when typical frequency division duplexing (FDD) or time division duplexing (TDD) are employed in a transceiver design. Although full duplex (FD) technology has enhanced the performance of the radio communication devices, the main challenge in full duplex communication is the leaking self-interference signal from the transmitter to the receiver. Different methods are employed to suppress the self-interference signal in digital and analog domains which are categorized as passive or active cancellations. These techniques are discussed in this thesis in order to understand from which point in the propagation path, the required signal for cancellation can be taken and how those techniques are employed in digital and analog domains. For having a good self-interference cancellation (SIC) both analog and digital cancellation techniques are needed since typical digital suppression method is low complex and somewhat limited. In this thesis, first we start with discussing about the full duplex technology and the reason why it has become popular in recent years and later full duplex deficiencies are examined. In the following chapters different cancellation methods are introduced and some results are provided in Chapter 5

Circuits and Systems for On-Chip RF Chemical Sensors and RF FDD Duplexers

Integrating RF bio-chemical sensors and RF duplexers helps to reduce cost and area in the current applications. Furthermore, new applications can exist based on the large scale integration of these crucial blocks. This dissertation addresses the integration of RF bio-chemical sensors and RF duplexers by proposing these initiatives. A low power integrated LC-oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity ε’r is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter (FDC). The imaginary relative permittivity ε”r increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop (ALL) is used to fix the amplitude and linearize the relation between the oscillator bias current and ε”r. The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling (CDS) is used to mitigate the impact of flicker noise, temperature variations and frequency drifts. A prototype is implemented in 0.18 µm CMOS process with total chip area of 6.24 mm^2 to operate in 1-6 GHz range using three dual bands LC oscillators. The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading. A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky SAW and BAW duplexers in 3G/4G cellular transceivers. A balancing network creates a replica of the transmitter signal for cancellation at the input of a single-ended low noise amplifier (LNA) to isolate the receive path from the transmitter. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra balun at the antenna side. The duplexer achieves around 50 dB TX-RX isolation within 1.6-2.2 GHz range up to 22 dBm. The cascaded noise figure of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in 0.18 µm CMOS process and occupy an active area of 0.35 mm^2

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

Ka-band full duplex system with electrical balance duplexer for 5G applications using SiGe BiCMOS technology

The current dominating communication system is 4G. However, with the increase in the data rate and in the number of users in the world, the 4G communication system has started to saturate and couldn’t manage to keep up with user demands and there is less room for progress at 4G systems. In search of finding a system that covers the future interests of users, a new communication scheme is being processed as 5G. The next generation systems require wider bandwidth, high spectral efficiency, and less latency. For these goals, designs with higher frequency and full-duplex operation mode have been started to gain attention. Developments in SiGe HBT technologies -higher fT and fmax- make them suitable for these challenges. Considering these trends which lead to the future of communication systems, in this thesis the design of Ka-band (25-32GHz) SiGe full duplex system with electrical balance duplexer for 5G applications is presented. This system is created by integrating. a duplexer, an LNA, and a PA. The electrical balance duplexer is realized by a hybrid transformer and a balancing network. The impedance of the antenna is mimicked by tuning the balancing network to provide high isolation between transmitter and receiver blocks. All the ports have better than 10dB return loss. Duplexer provides measured 39dB peak isolation at 28GHz, with 3.8dB insertion loss from the transmitter to the antenna and 4.7dB insertion loss from the antenna to receiver. The LNA achieves the measured gain of 15dB, NF of 3.5dB and OP1dB of 13.5dBm at 28GHz by including an input and an output BALUN transformer. The PA provides measured gain of 17dB and OP1dB of 14dBm at 28GH

SAW-Less Digitally-Assisted Receivers

Today’s wireless devices, like our smartphones, are able to handle multiple standards and bands for different applications, such as Bluetooth, Wi-Fi and data-voice communications. However, the cost of a modern transceiver is becoming mainly dominated by the large number of off-chip passive components, like Duplexers and SAW filters, needed to distinguish the desired signal among many interferences. Addressing the challenges that arise from the lack of RF filtering, a SAW-less architecture represents an interesting solution to reduce the platform complexity. This thesis proposes a feasible solution based on a SAW-less RF front-end able to meet the standard requirements and a digital system tailored to the RF path. The digital architecture, which represents the main topic of this thesis, is described in detail and experimentally tested to validate the proposed solutions

펄스에 의한 동적 부하 변조 기술을 이용한 고효율 선형 송신기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 서광석.STRONG push for longer battery life time and growing thermal concerns for the modern 3G/4G mobile terminals lead to an ever-growing need for higher efficiencies from the handset power amplifiers (PAs). Furthermore, as the modulation signal bandwidth is increased and more complex modulation schemes are introduced for higher data rate, the peak-to-average power ratio (PAPR) of signals increases and the PA requires more power back-off to meet the stringent linearity requirement. Therefore, the PA design has to address the challenging task of enhancing the efficiencies in the back-off power levels. In this dissertation, dynamic load modulation (DLM) technique is investigated to boost the efficiency of a PA in the back-off output power level. This technique increases the efficiency by adjusting the PA load impedance according to the magnitude of the envelope signal. It can be categorized into two types, continuous and discrete types. Continuous-type DLM PA changes load impedance continuously by changing the capacitance of varactors used in the load matching circuit. Although the continuous modulation of the load impedance may result in significant efficiency enhancement, difficulties on integration of varactors and complexities on linearization of the PA make it difficult to be applied to the handset PA applications. Discrete-type DLM PA switches the load impedance from one value to another using RF switches. This type has the advantage in the aspect of ease of integration and simplicity in linearization compared to the continuous-type DLM PA, which make it more suited to the handset PA applications. However, the overall efficiency enhancement is quite limited since the PA does not always operate under the optimal load conditions. To overcome the limitation of the existing DLM techniques, a new method of DLM, called pulsed dynamic load modulation (PDLM), is proposed to operate the PA near the optimum impedance across a continuous back-off power range while still benefiting from the advantages offered by the discrete-type DLM PA. PDLM PA combines the concept of Class-S PA with 1-bit discrete load switching. Analytical calculation using simplified equivalent model is well matched with simulation results. To prove the proposed concept, it is implemented by designing and fabricating a prototype PDLM PA at 837 MHz using a 0.32-μm silicon-on-insulator (SOI) CMOS process. The experimental results show the overall PAE improvement for high-PAPR signals such as LTE signals. Several issues caused by the PDLM technique are also discussed such as imperfect pulse tone termination effect and output noise spectrum due to pulse tones. Improving methods are proposed through the further analysis and evaluation. The proposed PA is compared to the envelope tracking (ET) PA which is commonly used to boost efficiency at the back-off output power. Since the proposed concept is realized with low-power control circuits unlike envelope tracking, which requires high-power circuits such as dc-dc converters and linear amplifiers, the PDLM PA concept of this work can provide a potential solution for high-efficiency PAs for the future mobile terminals using wideband modulation signals.Chapter 1. Introduction 1 Chapter 2. Dynamic Load Modulation Technique 8 2.1 Introduction 8 2.2 Continuous-type dynamic load modulation PA 9 2.3 Discrete-type dynamic load modulation PA 14 2.4 Implementation example 15 2.4.1 DLM PA Structure 16 2.4.2 Linearization 23 2.4.3 Experimental Results 25 2.4.4 Conclusion 31 2.5 Limitations 32 2.6 References 33 Chapter 3. A Pulsed Dynamic Load Modulation Technique for High-Efficiency Linear Transmitters 36 3.1 Introduction 36 3.2 Operation Principle of the PDLM PA 38 3.2.1 Concept of the PDLM PA 38 3.2.2 Theoretical Analysis of the PDLM PA 41 3.3 Circuit Design 47 3.3.1 2 stage CMOS PA design 49 3.3.2 High power RF switch design 59 3.3.3 PWM signal generator and switch driver 61 3.4 Experimental Results 63 3.5 Conclusion 76 3.6 References 77 Chapter 4. Discussions 83 4.1 Operation bandwidth of the PDLM PA 83 4.2 Spectral noise reduction method 87 4.3 References 91 Chapter 5. Conclusions 94 5.1 Research Summary 94 5.2 Future Works 95 Abstract in Korean 97 Publications 99Docto