Technological Integration in Printed Electronics

Conventional electronics requires the use of numerous deposition techniques (e.g. chemical vapor deposition, physical vapor deposition, and photolithography) with demanding conditions like ultra-high vacuum, elevated temperature and clean room facilities. In the last decades, printed electronics (PE) has proved the use of standard printing techniques to develop electronic devices with new features such as, large area fabrication, mechanical flexibility, environmental friendliness and—potentially—cost effectiveness. This kind of devices is especially interesting for the popular concept of the Internet of Things (IoT), in which the number of employed electronic devices increases massively. Because of this trend, the cost and environmental impact are gradually becoming a substantial issue. One of the main technological barriers to overcome for PE to be a real competitor in this context, however, is the integration of these non-conventional techniques between each other and the embedding of these devices in standard electronics. This chapter summarizes the advances made in this direction, focusing on the use of different techniques in one process flow and the integration of printed electronics with conventional systems

Integration of Ultrasonic Consolidation and Direct-Write to Fabricate an Embedded Electrical System Within a Metallic Enclosure

A research project was undertaken to integrate Ultrasonic Consolitation (UC) and Direct-Write (DW) technologies into a single apparatus to fabricate embedded electrical systems within an ultrasonically consolidated metallic enclosure. Process and design guidelines were developed after performing fundamental research on the operational capabilities of the implemented system. In order to develop such guidelines, numerous tests were performed on both UC and DW. The results from those tests, as well as the design and process guidelines for the fabrication of an embedded touch switch, can be used as a base for future research and experimentation on the UC-DW apparatus. The successful fabrication of an embedded touch switch proves the validity of the described design and process parameters and demonstrates the usefulness of this integration

Integrated 3D glass modules with high-Q inductors and thermal dissipation for RF front-end applications

The objectives of this research are to model, design, fabricate and validate high quality factor (Q > 100 at 2.4 GHz for 3-10 nH/mm2) inductors and innovative thermal structures with copper through-package vias to maintain low junction temperatures of < 85 oC in power amplifiers, and demonstrate ultra-thin fully-integrated dual-band (2.4 GHz/ 5GHz) WLAN modules with passive-active integration on ultra-thin glass substrates with double-side RF circuits and copper through-package vias (TPVs). Today’s RF subsystems are 2D single or multichip packages made of either organic laminates or LTCC (low temperature co-fired ceramic) substrates. The need for form-factor reduction in RF subsystems in both z and x-y direction has led to the evolution of embedded die-package architectures in thin laminates with dies facing up or down. This also reduces insertion loss and improves signal integrity by minimizing electromagnetic interference (EMI), package parasitics and routing issues. For further improvement in performance and miniaturization, glass is proposed as an ideal substrate for RF module integration. However, major design and fabrication challenges need to be addressed to achieve ultra-thin high Q RF components and also enable IC cooling to eliminate hotspots on glass substrates, which forms the key focus of this thesis.Ph.D

MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies

Development of sensors and non-destructive techniques to determine the performance of coatings in construction

The primary objective of this work was to examine and develop techniques for monitoring the degradation of Organically Coated Steel (OCS) in-situ. This included the detection of changes associated with the weathering to both the organic coating and metallic substrate. Initially, a review of current promising techniques was carried out however many were found to be unsuitable for this application and the adaptation of current techniques and the development of new techniques was considered. A brief concept investigation, based on initial testing and considerations, was used to determine a number of sensing techniques to examine. These included embedded, Resonant Frequency Identification (RFID), Magnetic Flux Leakage (MFL) and dielectric sensing. Each of these techniques were assessed for the application, prototyped, and tested against a range of samples to determine the accuracy and sensitivity of degradation detection provided. A range of poorly and highly durable coated samples were used in conjunction with accelerated weathering testing for this aim. Track based electronic printed sensors were presented as both a cut edge corrosion tracking and coating capacitance measurement method. While suffering somewhat from electrical paint compatibility issues both concepts showed merit in initial trials however the capacitive sensor ultimately proved insufficiently responsive to coating changes. The embedded, progressive failure-based, cut edge corrosion sensor was produced and tested in modern coating systems with moderate success. Novel applications of RFID and MLF techniques were considered and proved capable of detecting large changes in substrate condition due to significant corrosion. However, there was a lack of sufficient sensitivity when considering early-stage corrosion of durable modern OCS products. Finally, it was shown that a chipless antenna could be designed and optimised for novelly monitoring the changes to the dielectric properties of a paint layer due to degradation. However, ultimately this test, due to equipment requirements, lent itself more to lab testing than in-situ. Due to some of these limitations a different approach was considered in which the environmental factors influencing degradation were examined with the aim of relating these to performance across a building. It was observed that a combination of high humidity and the build-up of aggressive natural deposits contributed to high degradation rates in sheltered regions, such as building eaves, where microclimates were created. The build-up of deposits and their effect was presented as a key degradation accelerant during in-use service. A unique numerical simulation approach was developed to predict the natural washing, via rain impact and characteristics of the building analysed. This approach showed promise for determining areas unlikely to be naturally washed, and therefore subjected to a degradation accelerating, build-up of deposits. Given these understandings coated wetness sensors were considered as a realistic live-monitoring device capable of determining deposit build up and ultimately OCS lifetime

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (&lt;30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

Integration of optical interconnections and optoelectronic components in flexible substrates

Licht als informatiedrager voor datacommunicatie kende een ongezien succes in de laatste decennia. Wegens de lage verliezen en hoge datasnelheden hebben ze voor het overbruggen van lange afstanden hun elektrische tegenhangers reeds geruime tijd verdrongen. Deze trend zet zich ook voort voor korte afstand communicatie op printplaten. Naast zijn functie als informatiedrager, wordt licht ook gebruikt om een waaier aan fysische grootheden te meten. Ook hier heeft licht enkele significante voordelen t.o.v elektrische informatiedragers, waardoor optische sensoren wijdverspreid zijn. Een tweede duidelijke trend binnen de elektronica is het gebruik van flexibele printkaarten. Deze zijn veel dunner, lichter en betrouwbaarder dan de klassieke harde printkaarten, waardoor ze uiterst geschikt zijn voor draagbare toepassingen waar compactheid en een laag gewicht hoge vereisten zijn. De flexibiliteit van de printplaten laat ook toe hen te gebruiken op onvlakke oppervlakken en op bewegende onderdelen. Het doel van het gepresenteerde doctoraatswerk is de ontwikkeling van een nieuw technologieplatform dat bovengenoemde trends combineert. Alle bouwblokken van optische communicatie, gaande van actieve opto-elektronische componenten, aanstuurelektronica, golfgeleiderbaantjes en galvanische verbindingen tot optische koppelstructuren tussen de verschillende bouwblokken, worden zodanig gerealiseerd dat elke component flexibel is en geïntegreerd wordt in een dunne folie met een dikte van slechts 150µm. Op die manier bekomen we een flexibele folie met alle passieve en actieve onderdelen voor optische communicatie geïntegreerd met enkel een elektrische interface naar de buitenwereld, wat de aanvaarding en toepassing van deze technologie in de huidige elektronica aanzienlijk kan versnellen. Binnen het doctoraatswerk werden alle voorgestelde technologieën en processen gerealiseerd en geoptimaliseerd. Bovendien werden de optische verliezen, warmteaspecten, hoogfrequent gedrag, mechanisch gedrag en betrouwbaarheid van de technologie gekarakteriseerd en vergeleken met de huidige state-of-the-art

Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics

The fundamental motivation for this dissertation is to address the widening interconnect gap between integrated circuit (IC) demands and package substrates specifically for high frequency digital-RF systems applications. Moore's law for CMOS ICs predicts that transistor density on ICs will double approximately every 18 months. The current state-of-the-art in IC package substrates is at 20µm lines/spaces and 50-60µm microvia diameter using epoxy dielectrics with loss tangent above 0.01. The research targets are to overcome the barriers of current technologies and demonstrate a set of advanced materials and process technologies capable of 5-10µm lines and spaces, and 10-30µm diameter microvias in a multilayer 3-D wiring substrate using 10-25µm thin film dielectrics with loss tangent in the <0.005. The research elements are organized as follows with a clear focus on understanding and characterization of fundamental materials structure-processing-property relationships and interfaces to achieve the next generation targets. (a) Low CTE Core Substrate, (b) Low Loss Dielectrics with 25µm and smaller microvias, (c) Sub-10µm Width Cu Conductors, and (d) Integration of the various dielectric and conductor processes.Ph.D.Committee Chair: Tummala, Rao; Committee Member: Iyer, Mahadevan; Committee Member: Saxena, Ashok; Committee Member: Swaminathan, Madhavan; Committee Member: Wong, Chingpin