Flash-based security primitives: Evolution, challenges and future directions

Over the last two decades, hardware security has gained increasing attention in academia and industry. Flash memory has been given a spotlight in recent years, with the question of whether or not it can prove useful in a security role. Because of inherent process variation in the characteristics of flash memory modules, they can provide a unique fingerprint for a device and have thus been proposed as locations for hardware security primitives. These primitives include physical unclonable functions (PUFs), true random number generators (TRNGs), and integrated circuit (IC) counterfeit detection. In this paper, we evaluate the efficacy of flash memory-based security primitives and categorize them based on the process variations they exploit, as well as other features. We also compare and evaluate flash-based security primitives in order to identify drawbacks and essential design considerations. Finally, we describe new directions, challenges of research, and possible security vulnerabilities for flash-based security primitives that we believe would benefit from further exploration

High-Voltage Programmable Delta-Sigma Modulation Voltage-Control Circuit

Modern memory semiconductors require different internal voltages to accomplish the myriad of tasks that are required for operation. These internal voltages are multiples of the external voltage that is applied to the part. This multiple can be greater than one, as is the case with voltage pumps, less than one, as in the case of regulated supplies, and negative, as in the case of negative charge pumps. All of these potentials require control and regulation to ensure proper operation of the die. The control of the supply ensures that the required potentials are available when the die needs it. The regulation portion of the equation ensures that the desired potential is sufficient to meet the circuit needs and can react to changes in the circuit using the potential. This research explores the use of a Delta-Sigma Modulation-based circuit to control and regulate the operation of a voltage-generation circuit as well as introduce the ability to dynamically program the output voltage. What is presented in this thesis is the use of Delta-Sigma Modulation to sense, generate, and control the pumped wordline potentials necessary in a modern NAND memory device. These voltages generally consist of a read, erase, pass, and program potentials. The topology was chosen for voltage stability, superior response time when measured at the highest potential, and the ability to program the desired output potential depending on the circuit operation being performed. The proposed circuit was designed and fabricated using AMI’s 500 nm process through the MOSIS service (www.mosis.com). The chip performance has been evaluated and compared to the simulation results to verify accurate voltage generation over a wide input voltage and output response to changes in the input voltage. The control voltage was varied from 0.6 volts to 2.0 volts and the output voltages were measured to be 5.76 volts and 20.03 volts, respectively. The linearity of the output response was measured to average within 100 millivolts of the ideal. The response time of the DSM was also measured with good correlation to the simulation values

Designs for increasing reliability while reducing energy and increasing lifetime

In the last decades, the computing technology experienced tremendous developments. For instance, transistors' feature size shrank to half at every two years as consistently from the first time Moore stated his law. Consequently, number of transistors and core count per chip doubles at each generation. Similarly, petascale systems that have the capability of processing more than one billion calculation per second have been developed. As a matter of fact, exascale systems are predicted to be available at year 2020. However, these developments in computer systems face a reliability wall. For instance, transistor feature sizes are getting so small that it becomes easier for high-energy particles to temporarily flip the state of a memory cell from 1-to-0 or 0-to-1. Also, even if we assume that fault-rate per transistor stays constant with scaling, the increase in total transistor and core count per chip will significantly increase the number of faults for future desktop and exascale systems. Moreover, circuit ageing is exacerbated due to increased manufacturing variability and thermal stresses, therefore, lifetime of processor structures are becoming shorter. On the other side, due to the limited power budget of the computer systems such that mobile devices, it is attractive to scale down the voltage. However, when the voltage level scales to beyond the safe margin especially to the ultra-low level, the error rate increases drastically. Nevertheless, new memory technologies such as NAND flashes present only limited amount of nominal lifetime, and when they exceed this lifetime, they can not guarantee storing of the data correctly leading to data retention problems. Due to these issues, reliability became a first-class design constraint for contemporary computing in addition to power and performance. Moreover, reliability even plays increasingly important role when computer systems process sensitive and life-critical information such as health records, financial information, power regulation, transportation, etc. In this thesis, we present several different reliability designs for detecting and correcting errors occurring in processor pipelines, L1 caches and non-volatile NAND flash memories due to various reasons. We design reliability solutions in order to serve three main purposes. Our first goal is to improve the reliability of computer systems by detecting and correcting random and non-predictable errors such as bit flips or ageing errors. Second, we aim to reduce the energy consumption of the computer systems by allowing them to operate reliably at ultra-low voltage level. Third, we target to increase the lifetime of new memory technologies by implementing efficient and low-cost reliability schemes

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

Development and characterisation of a process technology for a 0.25µm SiGe:C RF-BiCMOS embedded flash memory

Integrating an embedded-flash memory module into a 0.25µm SiGe:C BiCMOS technology provides an important base for realising microelectronic systems that combine complex logic functionality with highest frequency analogue performance („System-on-Chip“). This dissertation presents for the first time an embedded flash memory module integrated in a 0.25µm SiGe:C BiCMOS process technology and describes the implementation into a process pilot line. The principle process flow and important process steps are described in detail, reviewing also the impact on the original BiCMOS process. The results are assessed geometrically by means of electron microscopy and electrically by characterisation of the developed electronic devices. The influence of important technological parameters is hereby investigated. The feasibility of the process for medium density memory production is finally demonstrated by a first 1-Mbit memory circuit that has been developed and produced based on the presented process technology