Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall

abstract: The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon. A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

A fully integrated 24-GHz phased-array transmitter in CMOS

This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to-null ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area

Ultra-broadband surface-normal coherent optical receiver with nanometallic polarizers

A coherent receiver that can demodulate high-speed in-phase and quadrature signals of light is an essential component for optical communication, interconnects, imaging, and computing. Conventional waveguide-based coherent receivers, however, exhibit large footprints, difficulty in coupling a large number of spatial channels efficiently, and limited operating bandwidth imposed by the waveguide-based optical hybrid. Here, we present a surface-normal coherent receiver with nanometallic-grating-based polarizers integrated directly on top of photodetectors without the need for an optical hybrid circuit. Using a fabricated device with the active section occupying a 70-{\mu}m-square footprint, we demonstrate demodulation of high-speed (up to 64 Gbaud) coherent signals in various formats. Moreover, ultra-broadband operation from 1260 nm to 1630 nm is demonstrated, thanks to the wavelength-insensitive nanometallic polarizers. To our knowledge, this is the first demonstration of a surface-normal homodyne optical receiver, which can easily be scaled to a compact two-dimensional arrayed device to receive highly parallelized coherent signals.Comment: 23 pages, 4 figures (main manuscript) + 4 pages, 2 figures (supporting info

High-speed and Robust Integrated Silicon Nanophotonics for On-Chip Interconnects

Optical interconnects offer advantages over electrical interconnects such as higher bandwidth, low power, reduced interconnects delay, and immunity to electro-magnetic interference and signal crosstalk. However, in order for optical interconnects to be widely adopted, the technology must be made cost effective and must be simple to implement with CMOS electronics. Silicon photonics offers a great promise due to its inexpensive material and its compatibility with the current CMOS fabrication technology. Moreover, Silicon as a platform has the ability to integrate with different types of the optical components such as photodetector, modulator, light source, and waveguide to form a photonics integrated circuit. The goal of this work is to develop and fabricate devices that utilize a hybrid electronic-photonic integration to enable high performance optoelectronic computing and communication systems that overcome the barriers of electronics and dramatically enhance the performance of circuits and systems. We experimentally demonstrate a novel broadband optical time division multiplexer (OTDM) on a silicon chip. The system has a footprint× 700 micrometer and is inherently broadband with a bandwidth of over 100nm making it suitable for high-speed optical networks on chip. Also, we propose and fabricate a novel design to demultiplex the high bit rates of OTDM data using two differentially operated 5Gb/s modulators. Moreover, we propose a high-speed hybrid optical-time-division-multiplexing (OTDM) and wavelength-division-multiplexing (WDM) system that seamlessly generates high bit-rate data (\u3e200Gbit/s) from a low speed (5Gbit/s) quantum-dot mode locked laser pulse source. By utilizing time and wavelength domains, the proposed design is a promising solution for high-speed, compact and low-power consumption optical networks on chip. And finally, we experimentally demonstrate a robust, low insertion loss, compact Silicon ring resonator electro-optic modulator for Binary Phase Shift Key (BPSK) coding/decoding that encodes data in the phase of light. Our design improves significantly over recently demonstrated PSK modulator designs in terms of insertion loss and stability

Aspectos de interconectividade dos moduladores de polímero

Orientador: Hugo Enrique Hernández-FigueroaTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: As interconexões ópticas e elétricas são de grande interese na area de encapsulamento de circuitos integrados híbridos fotônicos. Baixas perdas e banda larga são necessárias para o desenvolvimento de novas tecnologías na área. Nesta tese apresentan-se as seguintes contribuições originais: uma metodologia do modelamento de interconexões elétricas em encapsulamento de moduladores de polímero eletro-óptico, um dispositivo óptico compacto de banda larga para interconectar a plataforma de silício sobre isolante com a plataforma de filmes finos de polímero sobre silícioAbstract: Electrical and optical interconnects are of great interest for photonic integrated circuits with hybrid platforms. Low loss and wide band are essential for the development of new technologies in this area. In this thesis, we present the following original contributions: a methodology for modeling electrical ceramic interconnects inside an electrooptic polymer packaging, and a compact low-loss optical interconnect for the silicon-on-insulator platform to the thin-film polymer on silicon platformDoutoradoTelecomunicações e TelemáticaDoutor em Engenharia Elétrica07/2014-36CAPE

Silicon-organic hybrid electro-optical devices

Organic materials combined with strongly guiding silicon waveguides open the route to highly efficient electro-optical devices. Modulators based on the so-called silicon-organic hybrid (SOH) platform have only recently shown frequency responses up to 100 GHz, high-speed operation beyond 112 Gbit/s with fJ/bit power consumption. In this paper, we review the SOH platform and discuss important devices such as Mach-Zehnder and IQ-modulators based on the linear electro-optic effect. We further show liquid-crystal phase-shifters with a voltage-length product as low as V pi L = 0.06 V.mm and sub-mu W power consumption as required for slow optical switching or tuning optical filters and devices

Next Generation Silicon Photonic Transceiver: From Device Innovation to System Analysis

Silicon photonics is recognized as a disruptive technology that has the potential to reshape many application areas, for example, data center communication, telecommunications, high-performance computing, and sensing. The key capability that silicon photonics offers is to leverage CMOS-style design, fabrication, and test infrastructure to build compact, energy-efficient, and high-performance integrated photonic systems-on- chip at low cost. As the need to squeeze more data into a given bandwidth and a given footprint increases, silicon photonics becomes more and more promising. This work develops and demonstrates novel devices, methodologies, and architectures to resolve the challenges facing the next-generation silicon photonic transceivers. The first part of this thesis focuses on the topology optimization of passive silicon photonic devices. Specifically, a novel device optimization methodology - particle swarm optimization in conjunction with 3D finite-difference time-domain (FDTD), has been proposed and proven to be an effective way to design a wide range of passive silicon photonic devices. We demonstrate a polarization rotator and a 90◦ optical hybrid for polarization-diversity and phase-diversity communications - two important schemes to increase the communication capacity by increasing the spectral efficiency. The second part of this thesis focuses on the design and characterization of the next- generation silicon photonic transceivers. We demonstrate a polarization-insensitive WDM receiver with an aggregate data rate of 160 Gb/s. This receiver adopts a novel architecture which effectively reduces the polarization-dependent loss. In addition, we demonstrate a III-V/silicon hybrid external cavity laser with a tuning range larger than 60 nm in the C-band on a silicon-on-insulator platform. A III-V semiconductor gain chip is hybridized into the silicon chip by edge-coupling to the silicon chip. The demonstrated packaging method requires only passive alignment and is thus suitable for high-volume production. We also demonstrate all silicon-photonics-based transmission of 34 Gbaud (272 Gb/s) dual-polarization 16-QAM using our integrated laser and silicon photonic coherent transceiver. The results show no additional penalty compared to commercially available narrow linewidth tunable lasers. The last part of this thesis focuses on the chip-scale optical interconnect and presents two different types of reconfigurable memory interconnects for multi-core many-memory computing systems. These reconfigurable interconnects can effectively alleviate the memory access issues, such as non-uniform memory access, and Network-on-Chip (NoC) hot-spots that plague the many-memory computing systems by dynamically directing the available memory bandwidth to the required memory interface

Microwave Photonic Applications - From Chip Level to System Level

Die Vermischung von Mikrowellen- und optischen Technologien – Mikrowellenphotonik – ist ein neu aufkommendes Feld mit hohem Potential. Durch die Nutzung der Vorzüge beider Welten hat die Mikrowellenphotonik viele Anwendungsfälle und ist gerade erst am Beginn ihrer Erfolgsgeschichte. Der Weg für neue Konzepte, neue Komponenten und neue Anwendungen wird dadurch geebnet, dass ein höherer Grad an Integration sowie neue Technologien wie Silicon Photonics verfügbar sind. In diesem Werk werden zuerst die notwendigen grundlegenden Basiskomponenten – optische Quelle, elektro-optische Wandlung, Übertragungsmedium und opto-elektrische Wandlung – eingeführt. Mithilfe spezifischer Anwendungsbeispiele, die von Chipebene bis hin zur Systemebene reichen, wird der elektrooptische Codesign-Prozess veranschaulicht. Schließlich werden zukünftige Ausrichtungen wie die Unterstützung von elektrischen Trägern im Millimeterwellen- und THz-Bereich sowie Realisierungsoptionen in integrierter Optik und Nanophotonik diskutiert.The hybridization between microwave and optical technologies – microwave photonics – is an emerging field with high potential. Benefitting from the best of both worlds, microwave photonics has many use cases and is just at the beginning of its success story. The availability of a higher degree of integration and new technologies such as silicon photonics paves the way for new concepts, new components and new applications. In this work, first, the necessary basic building blocks – optical source, electro-optical conversion, transmission medium and opto-electrical conversion – are introduced. With the help of specific application examples ranging from chip level to system level, the electro-optical co-design process for microwave photonic systems is illustrated. Finally, future directions such as the support of electrical carriers in the millimeter wave and THz range and realization options in integrated optics and nanophotonics are discussed

System Level Analysis And Design For Wireless Inter-Chip Interconnection Communication Systems By Applying Advanced Wireless Communication Technologies

As the dramatic development of high speed integrated circuits has progressed, the 60 GHz silicon technology has been introduced to enable much faster computer systems and their corresponding applications. However, when signals are propagating at 60 GHz or higher frequencies on a PCB (Printed Circuit Board), the crosstalk among signal buses and devices, trace losses, and introduced parasitic capacitance and inductance between high density traces, become significant and may be severe enough such that the inter-chip communications will not be able to meet computer system signal specifications. High speed circuit signal integrity researchers in both electronic industries and academia have explored various methodologies to resolve these high frequency issues. Moreover, Intel is introducing Ultra Path Interconnect (UPI) for multi-core server systems, which demands more than 2.44 Tbps data rate between two CPUs, and 1.5 Tbps data rate for PCIe channel operation. Recently, the concept of the wireless inter/intra-chip interconnection (WIIC) technology was introduced [19, 23] for solving high frequency signal integrity issues. Here this dissertation mainly focuses on the inter-chip case while still using the WIIC designation for generality. Various WIIC technologies have been presented in the literature, which have focused on the investigations on Ultra Wide-Band (UWB), propagation channels, modulations, antennas, and power controls and interference. However, not much research has focused on a system level design, which includes the lowest two layers of the communication protocol in a WIIC system, namely, the physical, and data link layers. Also, the previously published literature has rarely reached the data rate at 100 Gbps or higher, and none of the prior research has obtained a spectrum utilization ratio of 4 bit/Hz or greater. In addition, currently existing research has not fully taken advantage of advanced and matured wireless communication technologies such as Orthogonal Frequency Division Multiplexing (OFDM), high order modulation, and Multiple-Input/Multiple-Output (MIMO) systems for increasing data rates and improving reliability, although the use of UWB [29], conventional FDMA or TDMA [39], and binary modulations including Binary Phase Shift Keying (BPSK) [22], On-Off Keying (OOK) [31], and Amplitude Shift Keying (ASK) [35] have been studied in previous research. In this dissertation, a complete WIIC system and a representative WIIC channel model have been developed by taking full advantages of advanced wireless communication techniques. First, this research has analyzed the potential of higher-order modulation, error correction, OFDM, and channel coding to the WIIC setting. Although MIMO, interleaving and scrambling are also analyzed but not included in the current version of the proposed WIIC system, they could be featured in hypothetically ideal future research to determine their potential benefits. Second, the performance of a proposed WIIC system has been analyzed in order to reach 100 Gbps data rate. Third, a 60 GHz WIIC channel based on metamaterial Electronic Band Gap (EBG) absorbers has been designed and analyzed using the numerical electromagnetics solver HFSS® and this EBG is integrated into the representative WIIC channel. Moreover, the impulse response of the WIIC channel is numerically extracted and is used for the system validation and testing. Furthermore, the system has been simulated with the WIIC channel and the wired PCB channel. It has been found that, the Bit Error Rate (BER) performance of the proposed WIIC channel is close to that of an AWGN channel with FEC, and much better than the AWGN channel without FEC, which means that the designed WIIC system and channel work properly within the frequency band centered at 60 GHz, while the wired PCB channel is almost cut off at 15 GHz or higher for the cases investigated. With only five or six layers on a PCB board, the WIIC system is able to provide 384 Gbps data rate theoretically with 12 GHz bandwidth, while the wired PCB counterpart needs more than 20 layers in order to avoid severe SI problems and to properly layout the Tbps channels. The current version of the WIIC system is able to provide 24 Gbps data rate with the bandwidth of 12 GHz using OFDM and QPSK