High-Resolution ADCs Design in Image Sensors

This paper presents design considerations for high-resolution and high-linearity ADCs for biomedical imaging ap-plications. The work discusses how to improve dynamic spec-ifications such as Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) in ultra-low power and high-resolution analog-to-digital converters (ADCs) including successive approximation register (SAR) for biomedical imaging application. The results show that with broad range of mismatch error, the SFDR is enhanced by about 10 dB with the proposed performance enhancement technique, which makes it suitable for high resolution image sensors sensing systems

High Linearity SAR ADC for Smart Sensor Applications

This paper presents capacitive array optimization technique to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for smart sensor application. Monte Carlo simulation results show that capacitive array optimization technique proposed can make the SFDR, SNDR and (Signal-to-Noise Ratio) SNR more concentrated, which means the differences between maximum value and minimum value of SFDR, SNDR and SNR are much smaller than the conventional calibration techniques, more stable performance enhancement can be achieved, and the averaged SFDR is improved from 72.9 dB to 91.1 dB by using the capacitive array optimization method, 18.2 dB improvement of SFDR is obtained with only little expense of digital logic circuits, which makes it good choice for high resolution and high linearity smart sensing systems

Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC

This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application. Behavioral Monte-Carlo simulations are applied to demonstrate the effect of the proposed method where no complex digital calibration algorithm or auxiliary calibration DAC needed. Simulation results show that with a mismatch error typical of modern technology, the SFDR is enhanced by more than 20 dB with the proposed technique for a 14-bit SAR ADC

Comparator Design in Sensors for Environmental Monitoring

This paper presents circuit design considerations of comparator in analog-to-digital converters (ADC) applied for a portable, low-cost and high performance nano-sensor chip which can be applied to detect the airborne magnetite pollution nano particulate matter (PM) for environmental monitoring. High-resolution ADC plays a vital important role in high perfor-mance nano-sensor, while high-resolution comparator is a key component in ADC. In this work, some important design issues related to comparators in analog-to-digital converters (ADCs) are discussed, simulation results show that the resolution of the comparator proposed can achieve 5µV , and it is appropriate for high-resolution application

Exploiting smallest error to calibrate non-linearity in SAR ADCs

This paper presents a statistics-optimised organisation technique to achieve better element matching in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in smart sensor systems. We demonstrate the proposed technique ability to achieve a significant improvement of around 23 dB on Spurious Free Dynamic Range (SFDR) of the ADC than the conventional, testing with a capacitor mismatch σu = 0.2% in a 14 bit SAR ADC system. For the static performance, the max root mean square (rms) value of differential nonlinearity (DNL) reduces from 1.63 to 0.20 LSB and the max rms value of integral nonlinearity (INL) reduces from 2.10 to 0.21 LSB. In addition, it is demonstrated that by applying grouping optimisation and strategy optimisation, the performance boosting on SFDR can be effectively achieved. Such great improvement on the resolution of the ADC only requires an off-line pre-processing digital part

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

LArPix: Demonstration of low-power 3D pixelated charge readout for liquid argon time projection chambers

We report the demonstration of a low-power pixelated readout system designed for three-dimensional ionization charge detection and digital readout of liquid argon time projection chambers (LArTPCs). Unambiguous 3D charge readout was achieved using a custom-designed system-on-a-chip ASIC (LArPix) to uniquely instrument each pad in a pixelated array of charge-collection pads. The LArPix ASIC, manufactured in 180 nm bulk CMOS, provides 32 channels of charge-sensitive amplification with self-triggered digitization and multiplexed readout at temperatures from 80 K to 300 K. Using an 832-channel LArPix-based readout system with 3 mm spacing between pads, we demonstrated low-noise ($<$500 e$^-$ RMS equivalent noise charge) and very low-power ($<$100 $\mu$W/channel) ionization signal detection and readout. The readout was used to successfully measure the three-dimensional ionization distributions of cosmic rays passing through a LArTPC, free from the ambiguities of existing projective techniques. The system design relies on standard printed circuit board manufacturing techniques, enabling scalable and low-cost production of large-area readout systems using common commercial facilities. This demonstration overcomes a critical technical obstacle for operation of LArTPCs in high-occupancy environments, such as the near detector site of the Deep Underground Neutrino Experiment (DUNE).Comment: 19 pages, 10 figures, 1 ancillary animation. V3 includes minor revisions based on referee comment

A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology

A novice advanced architecture of 8-bit analog todigital converter is introduced and analyzed in this work. Thestructure of proposed ADC is based on the sub-ranging ADCarchitecture in which a 4-bit resolution flash-ADC is utilized. Theproposed ADC architecture is designed by employing a comparatorwhich is equipped with common mode current feedback andgain boosting technique (CMFD-GB) and a residue amplifier. Theproposed 8 bits ADC structure can achieve the speed of 140 megasamplesper second. The proposed ADC architecture is designedat a resolution of 8 bits at 10 MHz sampling frequency. DNL andINL values of the proposed design are -0.94/1.22 and -1.19/1.19respectively. The ADC design dissipates a power of 1.24 mWwith the conversion speed of 0.98 ns. The magnitude of SFDRand SNR from the simulations at Nyquist input is 39.77 and 35.62decibel respectively. Simulations are performed on a SPICE basedtool in 90 nm CMOS technology. The comparison shows betterperformance for the proposed ADC design in comparison toother ADC architectures regarding speed, resolution and powerconsumption

A True 1V 1µW Biomedical Front End with Reconfigurable ADC for Self powered Smarter IoT Healthcare Systems

This work proposes an ultralow power highly linear analog front-end (AFE) with an input dynamic range from 200μVpp to 20mVpp. The system consists of a signal conditioning instrumentation amplifier (IA), two programmable gain amplifiers (PGA), a mixed signal automatic gain control (AGC), two sample and hold (S/H), a 10 bit successive approximation register (SAR) analog to digital converter (ADC), and a ΣΔ modulator with 10 bit effective number of bits (ENOB). A highly linear capacitively-coupled IA is achieved by increasing its feedback factor. Moreover, a transconductance (gm) cancellation technique is proposed for achieving a high common mode rejection ratio (CMRR). The conditioned signal is digitized using a SAR ADC for an input range of 200μVpp to 2mVpp, and, an opamp-shared ΣΔ ADC for an input range of 2mVpp to 20mVpp. The selection between the two ADCs is done by the AGC. The full system is designed using 1V supply in UMC 0.18μm CMOS technology. The AFE (IA and the two PGAs) achieves an overall linearity of more than 12 bits, for an input range of 200μVpp to 20mVpp while consuming 300nW with a bandwidth of 0.05 - 250Hz. The power consumption of the SAR ADC is 40nW while operating at a sampling frequency of 1KHz. The ΣΔ ADC consumes 300nW at a sampling frequency of 32KHz with an OSR of 32. The proposed system is intended to be powered by an energy scavenging circuit without compromising its own performance. The system was successfully tested for an ECG signal obtained from PTB database