This paper presents design considerations for high-resolution and high-linearity ADCs for biomedical imaging ap-plications. The work discusses how to improve dynamic spec-iﬁcations such as Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) in ultra-low power and high-resolution analog-to-digital converters (ADCs) including successive approximation register (SAR) for biomedical imaging application. The results show that with broad range of mismatch error, the SFDR is enhanced by about 10 dB with the proposed performance enhancement technique, which makes it suitable for high resolution image sensors sensing systems

Cen, Yuanjun

Fan, Hua

Feng, Quanyuan

Heidari, Hadi

Hu, Daqian

Li, Dagang

Maloberti, Franco

Yang, Jingxuan

English

Enlighten: Publications

 
 
 
 
 
Fan, H., Yang, J., Maloberti, F., Feng, Q., Li, D., Hu, D., Cen, Y. and 
Heidari, H. (2018) High-Resolution ADCs Design in Image Sensors. In: 
IEEE Latin American Symposium on Circuits and Systems (LASCAS 
2018), Puerto Vallarta, Mexico, 25-28 Feb 2018, ISBN 9781538623114 
(doi:10.1109/LASCAS.2018.8399935). 
 
This is the author’s final accepted version. 
 
There may be differences between this version and the published version. 
You are advised to consult the publisher’s version if you wish to cite from 
it. 
 
 
 
 
http://eprints.gla.ac.uk/153876/ 
     
 
 
 
 
 
 
Deposited on: 08 January 2018 
 
 
 
 
 
 
 
 
 
 
 
 
Enlighten – Research publications by members of the University of Glasgow 
http://eprints.gla.ac.uk 
High-Resolution ADCs Design in Image Sensors
Hua Fan1, Jingxuan Yang1, Franco Maloberti2, Quanyuan Feng3,
Dagang Li4, Daqian Hu4, Yuanjun Cen4, and Hadi Heidari5
1 State Key Laboratory of Electronic Thin Films and Integrated Devices,
University of Electronic Science and Technology of China, Chengdu, China (e-mail: fanhua7531@163.com)
2Department of Electrical, Computer, and Biomedical Engineering, University of Pavia 27100, Italy.
3School of Information Science and Technology, Southwest Jiaotong University, Chengdu 611756, China
4 Chengdu Sino Microelectronics Technology Co.,Ltd, Chengdu, China
5 Electronics and Nanoscale Engineering Division, School of Engineering, University of Glasgow, G12 8QQ, Glasgow, UK
Abstract—This paper presents design considerations for high-
resolution and high-linearity ADCs for biomedical imaging ap-
plications. The work discusses how to improve dynamic spec-
ifications such as Spurious Free Dynamic Range (SFDR) and
Signal-to-Noise-and-Distortion Ratio (SNDR) in ultra-low power
and high-resolution analog-to-digital converters (ADCs) including
successive approximation register (SAR) for biomedical imaging
application. The results show that with broad range of mismatch
error, the SFDR is enhanced by about 10 dB with the proposed
performance enhancement technique, which makes it suitable for
high resolution image sensors sensing systems.
Index Terms—Analog-to-Digital Converter, Successive Approx-
imation Register(SAR) ADC, Capacitive digital-to-analog con-
verter(DAC), Capacitor Mismatch Calibration, Image Sensing
Systems.
I. INTRODUCTION
Image Sensors are increasingly becoming “Key Devices”
for a broad range of products, such as medical, measuring
instruments, robot vision, specialized surveillance cameras,
broadcast and other industrial applications, etc, where wide
dynamic range, high sensitivity, high frame rate and low noise
are vital specifications to realize the best possible imaging
and sensing performance. For example, CMOS image sen-
sors can achieve over 100 dB of simultaneous-capture wide
dynamic range (SCWDR) [1]. In general, development of
high-resolution and wide dynamic range sensors is limited
by several factors, such as vertical and horizontal readout
circuit, analog to digital conversion, and data output from the
sensor, then putting forward high demands on column analog-
to-digital converters (ADCs), which is crucial unit to ensure
sufficient vertical readout period in image sensor as shown
in Fig. 1 [2], as results, high-performance ADCs have been
essential for the development of highly sensitive, stable, and
robust image sensor applications, furthermore, high perfor-
mance image sensors often require the ADCs with on-chip
capacitor mismatch calibration for the purpose of maintaining
high-resolution at a very low sampling rate. Usually, precision
of ADC in image sensors should be at least 12 bits, even 14-
bits [2]–[4].
Charge redistribution SAR ADC consumes much less power
compared with other types of ADC, in charge redistribution
SAR ADC, the limited factor is mostly due to the capacitor
mismatch. The resolution and its static and dynamic perfor-
Data Output
Signal Processor
Column ADCs
Readout Circuits
Memories
Signal Processor
Data Output
Pixel Pitch
D
riv
ers D
ri
v
er
s
Fig. 1. Block Diagram of Image Sensor [2].
mance mostly depend on how well the match of the capacitor
array. For SAR ADC, the ADC is composed of capacitors
sized to produce ratios in powers of 2, or binary ratios,
then errors of these ratios correspond to errors in conversion,
then the largest source of the ADC error is the process
variation of capacitor ratios. Several related self-calibration
techniques [5] and [6] were proposed to correct capacitor
ratio errors by employing additional auxiliary calibration sub-
DAC for measuring and storing the capacitor matching errors
into digital memory. During the subsequent conversion cy-
cles, these data are used to correct the digital output codes
digitally, since the foreground capacitor mismatch calibration
is only performed during power on, no extra latency or clock
cycles are introduced, but the auxiliary calibration DAC must
work all the time to compensate the mismatch error of each
capacitor, which consumes a lot of power. In this work, we
present a modified self-calibration method that eliminates this
limitation, auxiliary DAC is only applied to measure and
sort the capacitors, and does not work during the normal
conversion, as a result, power can be reduced during the
normal conversion. Simulation results show that with broad
range of mismatch error, the SFDR is enhanced by about 10
dB and the SNDR is 5 dB better with the proposed technique
for a 14-bit SAR ADC.
The remainder of this paper is organised as follows. Section
II describes circuit architecture. Section III gives detailed
description about the capacitor rearrangement technique pro-
posed, then Section IV compares the performance between
conventional and capacitor rearrangement technique proposed.
The conclusions are finally drawn in section V.
II. SAR ARCHITECTURE
Fig. 2 shows the block diagram of the conventional 14-
bit differential combined capacitor-resistor SAR ADC, binary
weighted capacitive DAC is employed as DAC for 6-bit main
DAC, the less significant bits are provided by a 8-bit resistor-
string sub DAC.
In SAR ADC, the error of the largest capacitor will be
huge compared to the small one, which is hard to predict
and control, accordingly, unit element architecture may be
an appropriate choice for the SAR ADC in consideration of
static and dynamic linearity [7]. Here, linearity is much more
important than the power consumption, for example, the power
of analog front end always reaches tens of mW [8], while the
power of ADC is always only an order of W [6], [9], [10].
 ! ! !" !
#$
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#%"
&'()*
&+,*
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&'(),
&+,,
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.
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%.!
01*23454671!898:452;1<;;8=>1.?1:893@
01,7A854671!898:452;1<;;8=>1.?1:893@
Fig. 2. A capacitor-resistor combined 14-bit SAR ADC architecture.
III. CAPACITOR REARRANGEMENT TECHNIQUE
In this section, the capacitor rearrangement technique will
be discussed based on the main 6-bit capacitive DAC of
capacitor-resistor combined SAR ADC in Fig. 2.
Fig. 3 shows the capacitor rearrangement technique pro-
posed. As well known, the conventional 6-bit binary weighted
charge redistribution DAC contains 64 unit capacitors, as
shown in Fig. 3(a), here, unit element architecture is applied
to ensure excellent static linearity, as shown in Fig. 3(b), then,
measuring values of all the 64 capacitors by the measurement
auxiliary DAC in Fig. 4, after measuring the values of all 64
CCC
C1
biggest
C2 C63 C64
smallest
C
64 Caps
CCC
64 Caps
C
C1 C64 C63 C32
CC
C2 C33
C16C32C C
64 Caps
CCC C
64 Caps
Fig. 3. (a) The conventional 6-bit binary capacitive array in Fig. 2; The
proposed capacitor rearrangement method applied to the 6-bit main capacitive
DAC features: (b) Split binary capacitive array into unary architecture;
(c)Sorting the 64 unit capacitors; (d) Re-arranging the capacitive array as
the final 6-bit capacitive array in Fig. 2.
capacitors, sorting the 64 capacitors from biggest to smallest,
in Fig. 3(c), C64 is the smallest and the C1 is the biggest one,
then the most important point is: the 64 capacitors (from C1 to
C64) are re-arranged by “one first and one last”, which means
the first capacitor C1 is followed by the last capacitor C64,
then the third capacitor C2 is followed by the last but one
capacitor C63, as shown in Fig. 3(d), finally, the re-ordered
capacitors proceed with the normal binary search conversion,
and the auxiliary measurement sub-DAC enters into idle mode
to save power.
   
   
!"#$%
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 3
 3
!"#$%
,-.!"#$%
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!"#$'
,-.!"#$'
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"456
78%9:;<;=>8 ?*?3;<9@8A@@?BC86D83?*:E
78'>F?<;=>8 ?*?3;<9@8A@@?BC86D83?*:E
Fig. 4. A capacitor-resistor combined 14-bit SAR ADC architecture with
capacitor rearrangement technique.
Finally, the block diagram of 14-bit SAR ADC with capaci-
tor rearrangement technique is shown in Fig. 4, auxiliary sub-
DAC is introduced to measure the value of each unit capacitor,
0 100 200 300 400 500
-120
-100
-80
-60
-40
-20
0
Input Frequency(kHz)
d
B
0 100 200 300 400 500
-120
-100
-80
-60
-40
-20
0
Input Frequency(kHz)
d
B
FFT of 14-bit SAR ADC( 
u
=0.1%)
0 100 200 300 400 500
-120
-100
-80
-60
-40
-20
0
Input Frequency(kHz)
d
B
FFT of 14-bit SAR ADC( 
u
=0.2%)
0 100 200 300 400 500
-120
-100
-80
-60
-40
-20
0
Input Frequency(kHz)
d
B
 !"#"$%&
'()*+,-./01234+567$
6'89*:,.;0&<
6=89*;:.+0&<
>=?<*+@.AB
Conventional
Fin=106.3 kHz@1MS/s
SFDR=82.4 dB
SNDR=77 dB
ENOB=12.5
C")D%)E(")FG
'()*+,-./01234+567$
6'89*;H.H0&<
6=89*;+./0&<
>=?<*++.H-
 !"#"$%&
'()*+,-./01234+567$
6'89*:-.;0&<
6=89*A@.-0&<
>=?<*+/.B
Fig. 5. FFT simulation results for 14-bit SAR ADC with respectively
Conventional and rearrangement technique with u=0.1% (left) and u=0.2%
(right).
but not works during normal conversion.
IV. SIMULATION RESULTS
To evaluate the improvement on the SFDR and SNDR of
14-bit capacitor-resistor combined ADC, a behavioral model
of a capacitor-resistor combined 14-bit SAR ADC is built
in Matlab. In the simulation, standard deviations of the unit
capacitors of 0.1%, 0.2%, 0.3%and 0.4% are considered to
cover as much diverse technologies as possible.
Fig. 5 and Fig. 6 present the power spectral density of the
ADC output with/without capacitor rearrangement technique,
where the input signal is a 106.3 kHz sinusoidal waveform
at the full-range reference voltage. When measured at 1
MSample/s without calibration, the ADC achieves a 71.3dB
SNDR and a 75.5 dB SFDR over the Nyquist bandwidth with
capacitor variation of 0.2%, capacitor rearrangement technique
can improve the SNDR from71.3 dB to 79.1 dB and can
improve the SFDR from 75.5 dB to 90.7 dB respectively.
Fig. 7, Fig. 8 and Fig. 9 and Fig. 10 show the SFDR and
SNDR results based on two switching techniques. A total of
500 Monte Carlo simulations were performed to obtain the
minimum, maximum as well as mean value of the SFDR and
SNDR.
Table I and Table II conclude 500 Monte Carlo SFDR
and SNDR simulation results, which show that 10 dB of
improvement about SFDR and 5 dB of improvement about
SNDR can be obtained in every case.
V. CONCLUSION
Capacitor mismatch calibration for SAR ADCs was pro-
posed, simulation results show that the mean value of SNDR
can be improved from 73.7 dB to 78.7 dB and the mean value
of SFDR can be improved from 79.4 dB to 89.6 dB with
u=0.2% by using the proposed technique.
0 100 200 300 400 500
-120
-100
-80
-60
-40
-20
0
Input Frequency(kHz)
d
B
FFT of 14-bit SAR ADC( 
u
=0.3%)
0 100 200 300 400 500
-120
-100
-80
-60
-40
-20
0
Input Frequency(kHz)
d
B
0 100 200 300 400 500
-120
-100
-80
-60
-40
-20
0
Input Frequency(kHz)
d
B
FFT of 14-bit SAR ADC( 
u
=0.4%)
0 100 200 300 400 500
-120
-100
-80
-60
-40
-20
0
Input Frequency(kHz)
d
B
Conventional
Fin=106.3 kHz@1MS/s
SFDR=76.8 dB
SNDR=70.9 dB
ENOB=11.48
 !"#"$%&
'()*+,-./01234+567$
6'89*:;.:0&<
6=89*;;.>0&<
?=@<*+A.B-
C")D%)E(")FG
'()*+,-./01234+567$
6'89*;,./0&<
6=89*-B.-0&<
?=@<*+,.-
 !"#"$%&
'()*+,-./01234+567$
6'89*:B.+0&<
6=89*;>.:0&<
?=@<*+A.+/
Fig. 6. FFT simulation results for 14-bit SAR ADC with respectively
Conventional and rearrangement technique with u=0.3% (left) and u=0.4%
(right).
 ! "! #! $! %! &!! &&!
!
 !
&!!
& !
'()*+,-.
/
0
1
2
34
SFDR of 14-bit SAR ADC( 
u
=0.1%)
 ! "! #! $! %! &!! &&!
!
 !
&!!
& !
'()*+,-.
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0
1
2
34
50 60 70 80 90 100 110
0
50
100
150
'()*+,-.
/
0
1
2
34
SFDR of 14-bit SAR ADC( 
u
=0.2%)
 ! "! #! $! %! &!! &&!
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 !
&!!
& !
'()*+,-.
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0
1
2
34
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(72:!;<%=>?@&='A4
B72+'()*.:# ;<C,-
B8D+'()*.:%%;<C,-
B682+'()*.:$ ; C,-
/02562370289
(72:!;<%=>?@&='A4
B72+'()*.:"%;<C,-
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B682+'()*.:#%;<C,-
FG0H046,
(72:!;<%=>?@&='A4
B72+'()*.:$#;EC,-
B8D+'()*.:&!!C,-
B682+'()*.:%";&C,-
FG0H046,
(72:!;<%=>?@&='A4
B72+'()*.:$!;$C,-
B8D+'()*.:%E;$C,-
B682+'()*.:$%;",-
Fig. 7. 500 Monte Carlo SFDR simulation results for 14-bit SAR ADC with
respectively Conventional and capacitor rearrangement with u=0.1% (left)
and u=0.2% (right)
VI. ACKNOWLEDGMENTS
The work of Hua Fan was supported by the National
Natural Science Foundation of China (NSFC) under Grant
61771111 and 61401066, as well as supported by China
Postdoctoral Science Foundation under grant 2017M612940
and Special Foundation of Sichuan Provincial Postdoctoral
TABLE I
500 MONTE CARLO SFDR SIMULATION SUMMARY
Conventional Proposed Improvement
(dB) (dB) (dB)
mean(SFDR)(u=0.1%) 85.5 96.1 10.6
mean(SFDR)(u=0.2%) 79.4 89.6 10.2
mean(SFDR)(u=0.3%) 75.9 86 10.1
mean(SFDR)(u=0.4%) 73.4 83.5 10.1
 ! "! #! $! %! &!!
!
 !
&!!
& !
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C
o
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n
ts
SFDR of 14-bit SAR ADC(
u
=0.3%)
 ! "! #! $! %! &!!
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 !
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0
1
2
34
 ! "! #! $! %! &!!
!
 !
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0
1
2
34
SFDR of 14-bit SAR ADC(
u
=0.4%)
 ! "! #! $! %! &!!
!
 !
&!!
& !
'()*+,-.
/
0
1
2
34
/02562370289
(72:!;<%=>?@&='A4
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EF0G046,
(72:!;<%=>?@&='A4
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/02562370289
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EF0G046,
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B72+'()*.:#<;$C,-
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Fig. 8. 500 Monte Carlo SFDR simulation results for 14-bit SAR ADC with
respectively Conventional and capacitor rearrangement with u=0.3% (left)
and u=0.4% (right)
 ! "! #! $! %!
!
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&!!
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SNDR(dB)
)
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u
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50 60 70 80 90
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u
=0.2%)
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Fig. 9. 500 Monte Carlo SNDR simulation results for 14-bit SAR ADC with
respectively Conventional and capacitor rearrangement with u=0.1% (left)
and u=0.2% (right)
Science Foundation;
The work of Quanyuan Feng was supported by the Na-
tional Natural Science Foundation of China (NSFC) under
Grant 61531016, supported by the project of Science and
Technology Support Program of Sichuan Province under Grant
TABLE II
500 MONTE CARLO SNDR SIMULATION SUMMARY
Conventional Proposed Improvement
(dB) (dB) (dB)
mean(SNDR)(u=0.1%) 78.8 82.7 3.9
mean(SNDR)(u=0.2%) 73.7 78.7 5
mean(SNDR)(u=0.3%) 70.4 75.7 5.3
mean(SNDR)(u=0.4%) 67.9 73.3 5.4
 ! "! #! $!
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0
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34
SNDR of 14-bit SAR ADC(
u
=0.3%)
 ! "! #! $!
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0
1
2
34
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SNDR of 14-bit SAR ADC(
u
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 ! "! #! $!
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Fig. 10. 500 Monte Carlo SNDR simulation results for 14-bit SAR ADC
with respectively Conventional and capacitor rearrangement with u=0.3%
(left) and u=0.4% (right)
2015GZ0103, and in part by the Sichuan Provincial Science
and Technology Important Projects under Grant 2017GZ0110.
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High-Resolution ADCs Design in Image Sensors

Crossref

High-resolution ADCs design in sensors

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     Fan, H., Yang, J., Maloberti, F., Feng, Q., Li, D., Hu, D., Cen, Y. and Heidari, H. (2018) High-Resolution ADCs Design in Image Sensors. In: IEEE Latin American Symposium on Circuits and Systems (LASCAS 2018), Puerto Vallarta, Mexico, 25-28 Feb 2018, ISBN 9781538623114 (doi:10.1109/LASCAS.2018.8399935).  This is the author’s final accepted version.  There may be differences between this version and the published version. You are advised to consult the publisher’s version if you wish to cite from it.     http://eprints.gla.ac.uk/153876/            Deposited on: 08 January 2018             Enlighten – Research publications by members of the University of Glasgow http://eprints.gla.ac.uk High-Resolution ADCs Design in Image SensorsHua Fan1, Jingxuan Yang1, Franco Maloberti2, Quanyuan Feng3,Dagang Li4, Daqian Hu4, Yuanjun Cen4, and Hadi Heidari51 State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology of China, Chengdu, China (e-mail: fanhua7531@163.com)2Department of Electrical, Computer, and Biomedical Engineering, University of Pavia 27100, Italy.3School of Information Science and Technology, Southwest Jiaotong University, Chengdu 611756, China4 Chengdu Sino Microelectronics Technology Co.,Ltd, Chengdu, China5 Electronics and Nanoscale Engineering Division, School of Engineering, University of Glasgow, G12 8QQ, Glasgow, UKAbstract—This paper presents design considerations for high-resolution and high-linearity ADCs for biomedical imaging ap-plications. The work discusses how to improve dynamic spec-ifications such as Spurious Free Dynamic Range (SFDR) andSignal-to-Noise-and-Distortion Ratio (SNDR) in ultra-low powerand high-resolution analog-to-digital converters (ADCs) includingsuccessive approximation register (SAR) for biomedical imagingapplication. The results show that with broad range of mismatcherror, the SFDR is enhanced by about 10 dB with the proposedperformance enhancement technique, which makes it suitable forhigh resolution image sensors sensing systems.Index Terms—Analog-to-Digital Converter, Successive Approx-imation Register(SAR) ADC, Capacitive digital-to-analog con-verter(DAC), Capacitor Mismatch Calibration, Image SensingSystems.I. INTRODUCTIONImage Sensors are increasingly becoming “Key Devices”for a broad range of products, such as medical, measuringinstruments, robot vision, specialized surveillance cameras,broadcast and other industrial applications, etc, where widedynamic range, high sensitivity, high frame rate and low noiseare vital specifications to realize the best possible imagingand sensing performance. For example, CMOS image sen-sors can achieve over 100 dB of simultaneous-capture widedynamic range (SCWDR) [1]. In general, development ofhigh-resolution and wide dynamic range sensors is limitedby several factors, such as vertical and horizontal readoutcircuit, analog to digital conversion, and data output from thesensor, then putting forward high demands on column analog-to-digital converters (ADCs), which is crucial unit to ensuresufficient vertical readout period in image sensor as shownin Fig. 1 [2], as results, high-performance ADCs have beenessential for the development of highly sensitive, stable, androbust image sensor applications, furthermore, high perfor-mance image sensors often require the ADCs with on-chipcapacitor mismatch calibration for the purpose of maintaininghigh-resolution at a very low sampling rate. Usually, precisionof ADC in image sensors should be at least 12 bits, even 14-bits [2]–[4].Charge redistribution SAR ADC consumes much less powercompared with other types of ADC, in charge redistributionSAR ADC, the limited factor is mostly due to the capacitormismatch. The resolution and its static and dynamic perfor-Data OutputSignal ProcessorColumn ADCsReadout CircuitsMemoriesSignal ProcessorData OutputPixel PitchDrivers DriversFig. 1. Block Diagram of Image Sensor [2].mance mostly depend on how well the match of the capacitorarray. For SAR ADC, the ADC is composed of capacitorssized to produce ratios in powers of 2, or binary ratios,then errors of these ratios correspond to errors in conversion,then the largest source of the ADC error is the processvariation of capacitor ratios. Several related self-calibrationtechniques [5] and [6] were proposed to correct capacitorratio errors by employing additional auxiliary calibration sub-DAC for measuring and storing the capacitor matching errorsinto digital memory. During the subsequent conversion cy-cles, these data are used to correct the digital output codesdigitally, since the foreground capacitor mismatch calibrationis only performed during power on, no extra latency or clockcycles are introduced, but the auxiliary calibration DAC mustwork all the time to compensate the mismatch error of eachcapacitor, which consumes a lot of power. In this work, wepresent a modified self-calibration method that eliminates thislimitation, auxiliary DAC is only applied to measure andsort the capacitors, and does not work during the normalconversion, as a result, power can be reduced during thenormal conversion. Simulation results show that with broadrange of mismatch error, the SFDR is enhanced by about 10dB and the SNDR is 5 dB better with the proposed techniquefor a 14-bit SAR ADC.The remainder of this paper is organised as follows. SectionII describes circuit architecture. Section III gives detaileddescription about the capacitor rearrangement technique pro-posed, then Section IV compares the performance betweenconventional and capacitor rearrangement technique proposed.The conclusions are finally drawn in section V.II. SAR ARCHITECTUREFig. 2 shows the block diagram of the conventional 14-bit differential combined capacitor-resistor SAR ADC, binaryweighted capacitive DAC is employed as DAC for 6-bit mainDAC, the less significant bits are provided by a 8-bit resistor-string sub DAC.In SAR ADC, the error of the largest capacitor will behuge compared to the small one, which is hard to predictand control, accordingly, unit element architecture may bean appropriate choice for the SAR ADC in consideration ofstatic and dynamic linearity [7]. Here, linearity is much moreimportant than the power consumption, for example, the powerof analog front end always reaches tens of mW [8], while thepower of ADC is always only an order of W [6], [9], [10]. ! ! !" !#$#%#%"&'()*&+,*&!-&'(),&+,,&'(),&'()*.// ! ! !%.!" !%.!01*23454671!898:452;1<;;8=>1.?1:893@01,7A854671!898:452;1<;;8=>1.?1:893@Fig. 2. A capacitor-resistor combined 14-bit SAR ADC architecture.III. CAPACITOR REARRANGEMENT TECHNIQUEIn this section, the capacitor rearrangement technique willbe discussed based on the main 6-bit capacitive DAC ofcapacitor-resistor combined SAR ADC in Fig. 2.Fig. 3 shows the capacitor rearrangement technique pro-posed. As well known, the conventional 6-bit binary weightedcharge redistribution DAC contains 64 unit capacitors, asshown in Fig. 3(a), here, unit element architecture is appliedto ensure excellent static linearity, as shown in Fig. 3(b), then,measuring values of all the 64 capacitors by the measurementauxiliary DAC in Fig. 4, after measuring the values of all 64CCCC1biggestC2 C63 C64smallestC64 CapsCCC64 CapsCC1 C64 C63 C32CCC2 C33C16C32C C64 CapsCCC C64 CapsFig. 3. (a) The conventional 6-bit binary capacitive array in Fig. 2; Theproposed capacitor rearrangement method applied to the 6-bit main capacitiveDAC features: (b) Split binary capacitive array into unary architecture;(c)Sorting the 64 unit capacitors; (d) Re-arranging the capacitive array asthe final 6-bit capacitive array in Fig. 2.capacitors, sorting the 64 capacitors from biggest to smallest,in Fig. 3(c), C64 is the smallest and the C1 is the biggest one,then the most important point is: the 64 capacitors (from C1 toC64) are re-arranged by “one first and one last”, which meansthe first capacitor C1 is followed by the last capacitor C64,then the third capacitor C2 is followed by the last but onecapacitor C63, as shown in Fig. 3(d), finally, the re-orderedcapacitors proceed with the normal binary search conversion,and the auxiliary measurement sub-DAC enters into idle modeto save power.      !"#$%!&'%!"#$'! (!&''!"#$'!"#$%!)*!)+ ,-.!"#$%,-.!"#$',-.!"#$%,-.!"#$'   /0/1/12 3 3!"#$%,-.!"#$%"1"4"456!"#$',-.!"#$'"1"4"45678%9:;<;=>8 ?*?3;<9@8A@@?BC86D83?*:E78'>F?<;=>8 ?*?3;<9@8A@@?BC86D83?*:EFig. 4. A capacitor-resistor combined 14-bit SAR ADC architecture withcapacitor rearrangement technique.Finally, the block diagram of 14-bit SAR ADC with capaci-tor rearrangement technique is shown in Fig. 4, auxiliary sub-DAC is introduced to measure the value of each unit capacitor,0 100 200 300 400 500-120-100-80-60-40-200Input Frequency(kHz)dB0 100 200 300 400 500-120-100-80-60-40-200Input Frequency(kHz)dBFFT of 14-bit SAR ADC( u=0.1%)0 100 200 300 400 500-120-100-80-60-40-200Input Frequency(kHz)dBFFT of 14-bit SAR ADC( u=0.2%)0 100 200 300 400 500-120-100-80-60-40-200Input Frequency(kHz)dB !"#"$%&'()*+,-./01234+567$6'89*:,.;0&<6=89*;:.+0&<>=?<*+@.ABConventionalFin=106.3 kHz@1MS/sSFDR=82.4 dBSNDR=77 dBENOB=12.5C")D%)E(")FG'()*+,-./01234+567$6'89*;H.H0&<6=89*;+./0&<>=?<*++.H- !"#"$%&'()*+,-./01234+567$6'89*:-.;0&<6=89*A@.-0&<>=?<*+/.BFig. 5. FFT simulation results for 14-bit SAR ADC with respectivelyConventional and rearrangement technique with u=0.1% (left) and u=0.2%(right).but not works during normal conversion.IV. SIMULATION RESULTSTo evaluate the improvement on the SFDR and SNDR of14-bit capacitor-resistor combined ADC, a behavioral modelof a capacitor-resistor combined 14-bit SAR ADC is builtin Matlab. In the simulation, standard deviations of the unitcapacitors of 0.1%, 0.2%, 0.3%and 0.4% are considered tocover as much diverse technologies as possible.Fig. 5 and Fig. 6 present the power spectral density of theADC output with/without capacitor rearrangement technique,where the input signal is a 106.3 kHz sinusoidal waveformat the full-range reference voltage. When measured at 1MSample/s without calibration, the ADC achieves a 71.3dBSNDR and a 75.5 dB SFDR over the Nyquist bandwidth withcapacitor variation of 0.2%, capacitor rearrangement techniquecan improve the SNDR from71.3 dB to 79.1 dB and canimprove the SFDR from 75.5 dB to 90.7 dB respectively.Fig. 7, Fig. 8 and Fig. 9 and Fig. 10 show the SFDR andSNDR results based on two switching techniques. A total of500 Monte Carlo simulations were performed to obtain theminimum, maximum as well as mean value of the SFDR andSNDR.Table I and Table II conclude 500 Monte Carlo SFDRand SNDR simulation results, which show that 10 dB ofimprovement about SFDR and 5 dB of improvement aboutSNDR can be obtained in every case.V. CONCLUSIONCapacitor mismatch calibration for SAR ADCs was pro-posed, simulation results show that the mean value of SNDRcan be improved from 73.7 dB to 78.7 dB and the mean valueof SFDR can be improved from 79.4 dB to 89.6 dB withu=0.2% by using the proposed technique.0 100 200 300 400 500-120-100-80-60-40-200Input Frequency(kHz)dBFFT of 14-bit SAR ADC( u=0.3%)0 100 200 300 400 500-120-100-80-60-40-200Input Frequency(kHz)dB0 100 200 300 400 500-120-100-80-60-40-200Input Frequency(kHz)dBFFT of 14-bit SAR ADC( u=0.4%)0 100 200 300 400 500-120-100-80-60-40-200Input Frequency(kHz)dBConventionalFin=106.3 kHz@1MS/sSFDR=76.8 dBSNDR=70.9 dBENOB=11.48 !"#"$%&'()*+,-./01234+567$6'89*:;.:0&<6=89*;;.>0&<?=@<*+A.B-C")D%)E(")FG'()*+,-./01234+567$6'89*;,./0&<6=89*-B.-0&<?=@<*+,.- !"#"$%&'()*+,-./01234+567$6'89*:B.+0&<6=89*;>.:0&<?=@<*+A.+/Fig. 6. FFT simulation results for 14-bit SAR ADC with respectivelyConventional and rearrangement technique with u=0.3% (left) and u=0.4%(right). ! "! #! $! %! &!! &&!! !&!!& !'()*+,-./01234SFDR of 14-bit SAR ADC( u=0.1%) ! "! #! $! %! &!! &&!! !&!!& !'()*+,-./0123450 60 70 80 90 100 110050100150'()*+,-./01234SFDR of 14-bit SAR ADC( u=0.2%) ! "! #! $! %! &!! &&!! !&!!& !'()*+,-./01234/02562370289(72:!;<%=>?@&='A4B72+'()*.:# ;<C,-B8D+'()*.:%%;<C,-B682+'()*.:$ ; C,-/02562370289(72:!;<%=>?@&='A4B72+'()*.:"%;<C,-B8D+'()*.:%E;<C,-B682+'()*.:#%;<C,-FG0H046,(72:!;<%=>?@&='A4B72+'()*.:$#;EC,-B8D+'()*.:&!!C,-B682+'()*.:%";&C,-FG0H046,(72:!;<%=>?@&='A4B72+'()*.:$!;$C,-B8D+'()*.:%E;$C,-B682+'()*.:$%;",-Fig. 7. 500 Monte Carlo SFDR simulation results for 14-bit SAR ADC withrespectively Conventional and capacitor rearrangement with u=0.1% (left)and u=0.2% (right)VI. ACKNOWLEDGMENTSThe work of Hua Fan was supported by the NationalNatural Science Foundation of China (NSFC) under Grant61771111 and 61401066, as well as supported by ChinaPostdoctoral Science Foundation under grant 2017M612940and Special Foundation of Sichuan Provincial PostdoctoralTABLE I500 MONTE CARLO SFDR SIMULATION SUMMARYConventional Proposed Improvement(dB) (dB) (dB)mean(SFDR)(u=0.1%) 85.5 96.1 10.6mean(SFDR)(u=0.2%) 79.4 89.6 10.2mean(SFDR)(u=0.3%) 75.9 86 10.1mean(SFDR)(u=0.4%) 73.4 83.5 10.1 ! "! #! $! %! &!!! !&!!& !'()*+,-.CountsSFDR of 14-bit SAR ADC(u=0.3%) ! "! #! $! %! &!!! !&!!& !'()*+,-./01234 ! "! #! $! %! &!!! !&!!& !'()*+,-./01234SFDR of 14-bit SAR ADC(u=0.4%) ! "! #! $! %! &!!! !&!!& !'()*+,-./01234/02562370289(72:!;<%=>?@&='A4B72+'()*.:" ;$C,-B8D+'()*.:$%;$C,-B682+'()*.:# ;%C,-EF0G046,(72:!;<%=>?@&='A4B72+'()*.:##;<C,-B8D+'()*.:$%;<C,-B682+'()*.:$"C,-/02562370289(72:!;<%=>?@&='A4B72+'()*.:"H;HC,-B8D+'()*.:$$;HC,-B682+'()*.:#H;<C,-EF0G046,(72:!;<%=>?@&='A4B72+'()*.:#<;$C,-B8D+'()*.:$";$C,-B682+'()*.:$H; ,-Fig. 8. 500 Monte Carlo SFDR simulation results for 14-bit SAR ADC withrespectively Conventional and capacitor rearrangement with u=0.3% (left)and u=0.4% (right) ! "! #! $! %!! !&!!& !'!!' !(!!( !SNDR(dB))*+,-.SNDR of 14-bit SAR ADC(u=0.1%)50 60 70 80 90050100150200250300350/0123456)*+,-. ! "! #! $! %!! !&!!& !'!!' !(!!( !/0123456)*+,-.SNDR of 14-bit SAR ADC(u=0.2%) ! "! #! $! %!! !&!!& !'!!' !(!!( !/0123456)*+,-.)*,78,-9*,:;<9,=!>?%@ABC&@/D.E9,3/0126=#&>(F45E:G3/0126=$?>(F45E8:,3/0126=#$>$F45HI*J*.84<9,=!>?%@ABC&@/D.E9,3/0126=#%>%F45E:G3/0126=$(>%F45E8:,3/0126=$'>#F45)*,78,-9*,:;<9,=!>?%@ABC&@/D.E9,3/0126=" >?F45E:G3/0126=$'>?F45E8:,3/0126=#(>#F45HI*J*.84<9,=!>?%@ABC&@/D.E9,3/0126=#?>#F45E:G3/0126=$!>#F45E8:,3/0126=#$>#F45Fig. 9. 500 Monte Carlo SNDR simulation results for 14-bit SAR ADC withrespectively Conventional and capacitor rearrangement with u=0.1% (left)and u=0.2% (right)Science Foundation;The work of Quanyuan Feng was supported by the Na-tional Natural Science Foundation of China (NSFC) underGrant 61531016, supported by the project of Science andTechnology Support Program of Sichuan Province under GrantTABLE II500 MONTE CARLO SNDR SIMULATION SUMMARYConventional Proposed Improvement(dB) (dB) (dB)mean(SNDR)(u=0.1%) 78.8 82.7 3.9mean(SNDR)(u=0.2%) 73.7 78.7 5mean(SNDR)(u=0.3%) 70.4 75.7 5.3mean(SNDR)(u=0.4%) 67.9 73.3 5.4 ! "! #! $!! !%!!% !&!!'()*+,-./01234SNDR of 14-bit SAR ADC(u=0.3%) ! "! #! $!! !%!!% !&!!'()*+,-./01234 ! "! #! $!! !%!!% !&!!'()*+,-./01234SNDR of 14-bit SAR ADC(u=0.4%) ! "! #! $!! !%!!% !&!!'()*+,-./012345607048,9:2;!<=>?@AB%?'C4D:2+'()*.;"$<>E,-DFG+'()*.;# <>E,-D8F2+'()*.;#H<HE,-/02I823:02FJ9:2;!<=>?@AB%?'C4D:2+'()*.; ><=E,-DFG+'()*.;#$<=E,-D8F2+'()*.;"#<>E,-/02I823:02FJ9:2;!<=>?@AB%?'C4D:2+'()*.;"%<>E,-DFG+'()*.;$!<>E,-D8F2+'()*.;#!<=E,-5607048,9:2;!<=>?@AB%?'C4D:2+'()*.;#%<=E,-DFG+'()*.;#$<=E,-D8F2+'()*.;# <#E,-Fig. 10. 500 Monte Carlo SNDR simulation results for 14-bit SAR ADCwith respectively Conventional and capacitor rearrangement with u=0.3%(left) and u=0.4% (right)2015GZ0103, and in part by the Sichuan Provincial Scienceand Technology Important Projects under Grant 2017GZ0110.REFERENCES[1] K. Nishimura, Y. Sato, J. Hirase, R. Sakaida, M. Yanagida, T. Tamaki,M. Takase, H. Kanehara, M. Murakami, and Y. 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