DESIGN OF A LOW POWER FLIP-FLOP USING CMOS DEEP SUBMICRON TECHNOLOGY

This paper enumerates low power, high speed design of flip-flop having less number of transistors and only one transistor being clocked by short pulse train which is true single phase clocking (TSPC) flip-flop. Compared to Conventional flip-flop, it has 5 Transistors and one transistor clocked, thus has lesser size and lesser power consumption. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The analysis for various flip flops and latches for power dissipation and propagation delays at 0.13μm and 0.35μm technologies is carried out. The leakage power increases as technology is scaled down. The leakage power is reduced by using best technique among all run time techniques viz. MTCMOS. Thereby comparison of different conventional flip-flops, latches and TSPC flip-flop in terms of power consumption, propagation delays and product of power dissipation and propagation delay with SPICE simulation results is presented

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies

This paper compares the effectiveness of different leakage control techniques in deep submicron (DSM) bulk CMOS technologies. Simulations show that the 3-5x increase in IOFF/µm per generation is offsetting the savings in switching energy obtained from technology scaling. We compare both the transistor IOFF reduction and ION degradation due to each technique for the 130nm-70nm technologies. Our results indicate that the effectiveness of leakage control techniques and the associated energy vs. delay tradeoffs depend on the ratio of switching to leakage energies for a given technology. We use our findings to design a 70nm low power word line driver scheme for a 256 entry, 64-bit register file (RF). As a result, the leakage (total) energy of the word line drivers is reduced by 3x(2.5x) and for the RF by up to 35%(25%) respectively

Power optimization techniques for advanced CPUs at physical implementation level

With the continuous growth and customer push to the requirements of embedded systems, smartphones, tablets, microcontrollers and the recent IoT (Internet of Things) market, more than ever the development of power efficient devices became a must, and highly crucial to achieve success in the digital design industry. Taking this into account, when developing modern advanced CPUs that are able to follow those industry requirements, power consumption is one of its key and most critical parameters. Meeting power consumption, operating frequency and silicon area, is a challenging task that usually implies in many trade-offs in the conception of an ASIC, as the strive for maximal power efficiency while offering good performance in small silicon area. This work presents the application of some power optimization techniques that can be performed on the context of physical implementation level with the help of advanced EDA tools’, in a modern advanced CPU design to be physically implemented in a 7nm process technology node. The investigation and exploration of the various possibilities and parameters variations offered by these tools can lead to PPA improvements, or even to the discovery of features or optimizations that doesn’t offer any improvements at the expense of considerable increase in processing runtime in the implementation flow. Characteristics like the use of different VT and channel length from multiple standard cell technology options and a multi bit flip-flop merging feature are addressed in this practical research work. The referred techniques are evaluated in terms of the collection of metrics, such as, power consumption, operating frequency, and silicon area, for different test cases.Com o crescimento contínuo e pressão de mercado das exigências para sistemas embarcados, smartphones, tablets, microcontroladores e o recente ramo de Internet das Coisas (em inglês IoT), mais do que nunca o desenvolvimento de dispositivos de baixo consumo de energia tornaram-se obrigatórios e cruciais para que se obtenha sucesso na indústria de design de circuitos digitais. Em vista disso, ao desenvolver modernas e avançadas Unidades Centrais de Processamento (em inglês CPUs) que são capazes de atender a essas exigências da indústria e do mercado, consumo de energia é um dos parâmetros chave e mais críticos para que isso se torne uma possibilidade. Satisfazer requisitos de consumo de energia, frequência de operação e área de silício simultaneamente, é uma tarefa desafiadora que normalmente implica num compromisso de escolha entre a preservação de uma característica em detrimento de outra na concepção de Circuitos Integrados de Aplicação Específica (em inglês ASIC). Este trabalho apresenta a aplicação de algumas técnicas de otimização de consumo de energia que podem ser adotadas no contexto de implementação física, com a ajuda de ferramentas avançadas de automação de projeto de circuitos digitais, em um CPU avançado para ser fisicamente implementado em tecnologia de processo de fabricação de 7 nm. A investigação e exploração das várias possibilidades e variação de parâmetros oferecidas por essas ferramentas podem levar a otimização em termos de Consumo de energia, Performance e Área (em inglês PPA), ou até para a descoberta de certas optimizações ou opções que não oferecem algum benefício, proporcionando apenas um alto aumento em tempo de processamento no fluxo de implementação. Características como o uso de diferentes opções de Tensão de Limiar de transistor (em inglês VT), de comprimento de canal a partir de múltiplas opções de células padrão (em inglês standard cells) e a opção de utilização de flip-flops de multíplos bits são exploradas nesse projeto de graduação. As técnicas referidas são avaliadas em termos de métricas, como consumo de energia, frequência de operação e área de silício, para diferentes casos de teste

Proposal for a 3.3V/5V Low Leakage High Temperature Digital Cell Library using Stacked Transistors

The objective of this research is to propose a method for developing a low leakage digital cell library capable of performing at extreme temperatures of up to 275C. The leakage current at extreme temperatures is a dominant factor and plays an important role in determining the circuit performance. A method of stacking low threshold voltage NMOS transistors over regular NMOS transistors has proven to reduce the leakage currents at extreme temperatures without much area penalty and loss in performance. The stacked NMOS transistors were fabricated and leakage data was measured on silicon. The 1.3um stacked NMOS device at 3.3 Volts supply voltage and 1.6um stacked NMOS device at 5 Volts supply voltage, had excellent Ion/Ioff ratios at 275C. The stacked NMOS transistors exhibited up to two orders of magnitude improvement in Ion/Ioff ratios over regular threshold NMOS transistors. Three basic combinational gates - Inverter, 3-input NAND and 3-input NOR gates with stacked NMOS transistors were tested on silicon for their Voltage Transfer Characteristic curves and these exhibited very little shift in the switching thresholds at temperatures of 275C compared to identically sized regular NMOS combinational gates.School of Electrical & Computer Engineerin

Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits

In nanometer-scale CMOS technology, leakage power has become a major component of the total power dissipation due to the downscaling of threshold voltage and gate oxide thickness. The leakage power consumption has received even more attention by increasing demand for mobile devices. Since mobile devices spend a majority of their time in a standby mode, the leakage power savings in standby state is critical to extend battery lifetime. For this reason, low power has become a major factor in designing CMOS circuits. In this dissertation, we propose a novel transistor reordering methodology for leakage reduction. Unlike previous technique, the proposed method provides exact reordering rules for minimum leakage formation by considering all leakage components. Thus, this method formulates an optimized structure for leakage reduction even in complex CMOS logic gate, and can be used in combination with other leakage reduction techniques to achieve further improvement. We also propose a new standby leakage reduction methodology, leakage-aware body biasing, to overcome the shortcomings of a conventional Reverse Body Biasing (RBB) technique. The RBB technique has been used to reduce subthreshold leakage current. Therefore, this technique works well under subthreshold dominant region even though it has intrinsic structural drawbacks. However, such drawbacks cannot be overlooked anymore since gate leakage has become comparable to subthreshold leakage in nanometer-scale region. In addition, BTBT leakage also increases with technology scaling due to the higher doping concentration applied in each process technology. In these circumstances, the objective of leakage minimization is not a single leakage source but the overall leakage sources. The proposed leakage-aware body biasing technique, unlike conventional RBB technique, considers all major leakage sources to minimize the negative effects of existing body biasing approach. This can be achieved by intelligently applying body bias to appropriate CMOS network based on its status (on-/off-state) with the aid of a pin/transistor reordering technique

Functional unit selection in microprocessors for low power

Master'sMASTER OF ENGINEERIN

Micro-architecture level low power design for microprocessors

Ph.DDOCTOR OF PHILOSOPH