Comparison of multi-layer bus interconnection and a network on chip solution

Abstract. This thesis explains the basic subjects that are required to take in consideration when designing a network on chip solutions in the semiconductor world. For example, general topologies such as mesh, torus, octagon and fat tree are explained. In addition, discussion related to network interfaces, switches, arbitration, flow control, routing, error avoidance and error handling are provided. Furthermore, there is discussion related to design flow, a computer aided designing tools and a few comprehensive researches. However, several networks are designed for the minimum latency, although there are also versions which trade performance for decreased bus widths. These designed networks are compared with a corresponding multi-layer bus interconnection and both synthesis and register transfer level simulations are run. For example, results from throughput, latency, logic area and power consumptions are gathered and compared. It was discovered that overall throughput was well balanced with the network on chip solutions, although its maximum throughput was limited by protocol conversions. For example, the multi-layer bus interconnection was capable of providing a few times smaller latencies and higher throughputs when only a single interface was injected at the time. However, with parallel traffic and high-performance requirements a network on chip solution provided better results, even though the difference decreased when performance requirements were lower. Furthermore, it was discovered that the network on chip solutions required approximately 3–4 times higher total cell area than the multi-layer bus interconnection and that resources were mainly located at network interfaces and switches. In addition, power consumption was approximately 2–3 times higher and was mostly caused by dynamic consumption.Monitasoisen väyläarkkitehtuurin ja tietokoneverkkomaisen ratkaisun vertailua. Tiivistelmä. Tutkielmassa käsitellään tärkeimpiä aihealueita, jotka tulee huomioida suunniteltaessa tietokoneverkkomaisia väyläratkaisuja puolijohdemaailmassa. Esimerkiksi yleiset rakenteet, kuten verkko-, torus-, kahdeksankulmio- ja puutopologiat käsitellään lyhyesti. Lisäksi alustetaan verkon liitäntäkohdat, kytkimet, vuorottelu, vuon hallinta, reititys, virheiden välttely ja -käsittely. Lopuksi kerrotaan suunnitteluvuon oleellisimmat välivaiheet ja niihin soveltuvia kaupallisia työkaluja, sekä käsitellään lyhyesti muutaman aiemman julkaisun tuloksia. Tutkielmassa käytetään suunnittelutyökalua muutaman tietokoneverkkomaisen ratkaisun toteutukseen ja tavoitteena on saavuttaa pienin mahdollinen latenssi. Toisaalta myös hieman suuremman latenssin versioita suunnitellaan, mutta pienemmillä väylänleveyksillä. Lisäksi suunniteltuja tietokoneverkkomaisia ratkaisuja vertaillaan perinteisempään monitasoiseen väyläarkkitehtuuriin. Esimerkiksi synteesi- ja simulaatiotuloksia, kuten logiikan vaatimaa pinta-alaa, tehonkulutusta, latenssia ja suorituskykyä, vertaillaan keskenään. Tutkielmassa selvisi, että suunnittelutyökalulla toteutetut tietokoneverkkomaiset ratkaisut mahdollistivat tasaisemman suorituskyvyn, joskin niiden suurin saavutettu suorituskyky ja pienin latenssi määräytyivät protokollan käännöksen aiheuttamasta viiveestä. Tutkielmassa havaittiin, että perinteisemmillä menetelmillä saavutettiin noin kaksi kertaa suurempi suorituskyky ja pienempi latenssi, kun verkossa ei ollut muuta liikennettä. Rinnakkaisen liikenteen lisääntyessä tietokoneverkkomainen ratkaisu tarjosi keskimäärin paremman suorituskyvyn, kun sille asetetut tehokkuusvaateet olivat suuret, mutta suorituskykyvaatimuksien laskiessa erot kapenivat. Lisäksi huomattiin, että tietokoneverkkomaisten ratkaisujen käyttämä pinta-ala oli noin 3–4 kertaa suurempi kuin monitasoisella väyläarkkitehtuurilla ja että resurssit sijaitsivat enimmäkseen verkon liittymäkohdissa ja kytkimissä. Lisäksi tehonkulutuksen huomattiin olevan noin 2–3 kertaa suurempi, joskin sen havaittiin koostuvan pääosin dynaamisesta kulutuksesta

The SANDRA project: cooperative architecture/compiler technology for embedded real-time streaming applications

The convergence of digital television, Internet access, gaming, and digital media capture and playback stresses the importance of high-quality and high-performance video and graphics processing. The SANDRA project, a collaboration between Philips Research and INRIA, develops a consistent and efficient system design approach for regular, real-time constrained stream processing. The project aims at providing a system template with its associated compiler chain and application development framework, enabling an early validation of both the functional and the non-functional requirements of the application at every system design stage

Engineering auf atomarer Skala von HfO2-basierten Dielektrika für künftige DRAM Anwendung

Modern dielectrics in combination with appropriate metal electrodes have a great potential to solve many difficulties associated with continuing miniaturization process in the microelectronic industry. One significant branch of microelectronics incorporates dynamic random access memory (DRAM) market. The DRAM devices scaled for over 35 years starting from 4 kb density to several Gb nowadays. The scaling process led to the dielectric material thickness reduction, resulting in higher leakage current density, and as a consequence higher power consumption. As a possible solution for this problem, alternative dielectric materials with improved electrical and material science parameters were intensively studied by many research groups. The higher dielectric constant allows the use of physically thicker layers with high capacitance but strongly reduced leakage current density. This work focused on deposition and characterization of thin insulating layers. The material engineering process was based on Si cleanroom compatible HfO2 thin films deposited on TiN metal electrodes. A combined materials science and dielectric characterization study showed that Ba added HfO2 (BaHfO3) films and Ti added BaHfO3 (BaHf0.5Ti0.5O3) layers are promising candidates for future generation of state of the art DRAMs. In especial a strong increase of the dielectric permittivity k was achieved for thin films of cubic BaHfO3 (k~38) and BaHf0.5Ti0.5O3 (k~90) with respect to monoclinic HfO2 (k~19). Meanwhile the CET values scaled down to 1 nm for BaHfO3 and ~0.8 nm for BaHf0.5Ti0.5O3 with respect to HfO2 (CET=1.5 nm). The Hf4+ ions substitution in BaHfO3 by Ti4+ ions led to a significant decrease of thermal budget from 900°C for BaHfO3 to 700°C for BaHf0.5Ti0.5O3. Future studies need to focus on the use of appropriate metal electrodes (high work function) and on film deposition process (homogeneity) for better current leakage control.Moderne Dielektrika in Verbindung mit geeigneten Metallelektroden haben großes Potential um viele Schwierigkeiten mit dem voranschreitenden Minituarisierungsprozess in der Mikroelektronik zu lösen. Ein wesentlicher Bestandteil der Mikroelektronik beinhaltet die Entwicklung von random access memory (DRAM). Diese begann vor über 35 Jahren mit Speichergrößen von 4kb, welche mittlerweile in den Bereich von mehreren Gigabytes vorangetrieben wurde. Daraus resultierte eine zunehmende Reduzierung der dieelektrischen Materialdicken, welche zu höheren Leckstromdichten und so zu einem erhöhten Leistungsverbrauch führte. Als mögliche Lösung werden alternative Dielektrika mit verbesserten elektrischen und materialspezifischen Eigenschaften von vielen Forschungsgruppen intensiv untersucht. Materialien mit höheren dielektrischen Konstanten ermöglichen die Verwendung von höheren Schichtdicken mit hohen Kapazitäten, jedoch mit vergleichsweise verringerten Leckstromdichten. Die vorliegende Arbeit beschäftigt sich mit der Deposition und Charakterisierung von dünnen isolierenden Schichten. Die Werkstoffkunde basierte auf dünnen HfO2 – Schichten die auf TiN – Metallelektroden abgeschieden wurden. Untersuchungen der materialspezifischen und dielektrischen Eigenschaften haben gezeigt, dass Ba-dotierte HfO2 Schichten (BaHfO3) und Ti-dotierte BaHfO3 Schichten (BaHf0.5Ti0.5O3) vielversprechende Kandidaten für die zukünftige Generation von DRAMs sind. Ein starkes Ansteigen der dielektrischen Permettivität konnte für dünne Schichten aus kubischem BaHfO3 (k~38) und BaHf0.5Ti0.5O3 (k~90) im Vergleich zu monoklinen HfO2 (k~19) erreicht werden. Mittlerweile sanken die CET-Werte bis auf 1 nm für BaHfO3 und ~0.8 nm für BaHf0.5Ti0.5O3 im Vergleich zu HfO2 (CET=1.5 nm). Die Substitution der Hf4+ - Ionen durch Ti4+ - Ionen in BaHfO3 führte zu einer signifikaten Absenkung des thermischen Budgets von 900°C für BaHfO3 zu 700°C für BaHf0.5Ti0.5O3. Zukünftige Untersuchungen haben zur Aufgabe die Leckstromkontrolle über passende Metallelektroden (höhere Austrittsarbeit) und einen Depositionsprozess mit verbesserter Homogenität zu verbessern

Comparison of the performance of 3G security algorithms in the NAS layer

Cryptographic functionality implementation approaches have evolved over time, first, for running security software on a general-purpose processor, second, employing a separate security co-processor ,and third, using built-in hardware acceleration for security that is a part of a multi-core CPU system. The aim of this study is to do performance tests in order to examine the boost provided by accelerating KASUMI cryptographic functions on a multi-core Cavium OCTEON processor over the same non-accelerating cryptographic algorithm implemented in software. Analysis of the results shows that the KASUMI SW implementation is much slower than the KASUMI HW-based implementation and this difference increases gradually as the packet size is doubled. In detailed comparisons between the encryption and decryption functions, the result indicates that at a lower data rate, neither of the KASUMI implementations shows much difference between encryption or decryption processing, regardless of the increase in the number of data packets that are being processed. When all the 16 cores of the OCTEAN processor are populated, as the number of core increases, the number of processing cycles decreases accordingly. Another observation was that when the number of cores in use exceeds 5 cores, it doesn’t make much difference to the number of decrease of processing cycles. This work illustrates the potential that up to sixteen cnMIPS cores integrated into a single-chip OCTEON processor provides for HW- and SW-based KASUMI implementations.fi=Opinnäytetyö kokotekstinä PDF-muodossa.|en=Thesis fulltext in PDF format.|sv=Lärdomsprov tillgängligt som fulltext i PDF-format

High Performance Multiview Video Coding

Following the standardization of the latest video coding standard High Efficiency Video Coding in 2013, in 2014, multiview extension of HEVC (MV-HEVC) was published and brought significantly better compression performance of around 50% for multiview and 3D videos compared to multiple independent single-view HEVC coding. However, the extremely high computational complexity of MV-HEVC demands significant optimization of the encoder. To tackle this problem, this work investigates the possibilities of using modern parallel computing platforms and tools such as single-instruction-multiple-data (SIMD) instructions, multi-core CPU, massively parallel GPU, and computer cluster to significantly enhance the MVC encoder performance. The aforementioned computing tools have very different computing characteristics and misuse of the tools may result in poor performance improvement and sometimes even reduction. To achieve the best possible encoding performance from modern computing tools, different levels of parallelism inside a typical MVC encoder are identified and analyzed. Novel optimization techniques at various levels of abstraction are proposed, non-aggregation massively parallel motion estimation (ME) and disparity estimation (DE) in prediction unit (PU), fractional and bi-directional ME/DE acceleration through SIMD, quantization parameter (QP)-based early termination for coding tree unit (CTU), optimized resource-scheduled wave-front parallel processing for CTU, and workload balanced, cluster-based multiple-view parallel are proposed. The result shows proposed parallel optimization techniques, with insignificant loss to coding efficiency, significantly improves the execution time performance. This , in turn, proves modern parallel computing platforms, with appropriate platform-specific algorithm design, are valuable tools for improving the performance of computationally intensive applications

A Proposal for a Three Detector Short-Baseline Neutrino Oscillation Program in the Fermilab Booster Neutrino Beam

A Short-Baseline Neutrino (SBN) physics program of three LAr-TPC detectors located along the Booster Neutrino Beam (BNB) at Fermilab is presented. This new SBN Program will deliver a rich and compelling physics opportunity, including the ability to resolve a class of experimental anomalies in neutrino physics and to perform the most sensitive search to date for sterile neutrinos at the eV mass-scale through both appearance and disappearance oscillation channels. Using data sets of 6.6e20 protons on target (P.O.T.) in the LAr1-ND and ICARUS T600 detectors plus 13.2e20 P.O.T. in the MicroBooNE detector, we estimate that a search for muon neutrino to electron neutrino appearance can be performed with ~5 sigma sensitivity for the LSND allowed (99% C.L.) parameter region. In this proposal for the SBN Program, we describe the physics analysis, the conceptual design of the LAr1-ND detector, the design and refurbishment of the T600 detector, the necessary infrastructure required to execute the program, and a possible reconfiguration of the BNB target and horn system to improve its performance for oscillation searches.Comment: 209 pages, 129 figure

Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA

This thesis presents a new architecture for the reliable implementation of the symmetric-key algorithm Advanced Encryption Standard (AES) in Field Programmable Gate Arrays (FPGAs). Since FPGAs are prone to soft errors caused by radiation, and AES is highly sensitive to errors, reliable architectures are of significant concern. Energetic particles hitting a device can flip bits in FPGA SRAM cells controlling all aspects of the implementation. Unlike previous research, heterogeneous error detection techniques based on properties of the circuit and functionality are used to provide adequate reliability at the lowest possible cost. The use of dual ported block memory for SubBytes, duplication for the control circuitry, and a new enhanced parity technique for MixColumns is proposed. Previous parity techniques cover single errors in datapath registers, however, soft errors can occur in the control circuitry as well as in SRAM cells forming the combinational logic and routing. In this research, propagation of single errors is investigated in the routed netlist. Weaknesses of the previous parity techniques are identified. Architectural redesign at the register-transfer level is introduced to resolve undetected single errors in both the routing and the combinational logic. Reliability of the AES implementation is not only a critical issue in large scale FPGA-based systems but also at both higher altitudes and in space applications where there are a larger number of energetic particles. Thus, this research is important for providing efficient soft error resistant design in many current and future secure applications

Architectures and Design Automation for Photonic Networks On Chip

Chip-scale photonics has emerged as an exciting field which can potentially solve many of the problems plaguing the high-performance computing industry, from large-scale to embedded. In theory, photonics is a superior communication medium because of its higher bandwidth density using wave-division multiplexing and bandwidth-power translucency to distance traveled. In practice, physical-layer design and engineering issues such as optical loss, crosstalk, and packaging have slowed its entry into widespread adoption at the chip and board scale. In this work, we present these issues and potential design improvements. The major contributions, however, are the tools and methods we have developed for the design of photonic interconnection networks, including a system-level simulator and CAD and modeling environment for layout, both of which are publicly available to the research community