Investigation into voltage and process variation-aware manufacturing test

Increasing integration and complexity in IC design provides challenges for manufacturing testing. This thesis studies how process and supply voltage variation influence defect behaviour to determine the impact on manufacturing test cost and quality. The focus is on logic testing of static CMOS designs with respect to two important defect types in deep submicron CMOS: resistive bridges and full opens. The first part of the thesis addresses testing for resistive bridge defects in designs with multiple supply voltage settings. To enable analysis, a fault simulator is developed using a supply voltage-aware model for bridge defect behaviour. The analysis shows that for high defect coverage it is necessary to perform test for more than one supply voltage setting, due to supply voltage-dependent behaviour. A low-cost and effective test method is presented consisting of multi-voltage test generation that achieves high defect coverage and test set size reduction without compromise to defect coverage. Experiments on synthesised benchmarks with realistic bridge locations validate the proposed method.The second part focuses on the behaviour of full open defects under supply voltage variation. The aim is to determine the appropriate value of supply voltage to use when testing. Two models are considered for the behaviour of full open defects with and without gate tunnelling leakage influence. Analysis of the supply voltage-dependent behaviour of full open defects is performed to determine if it is required to test using more than one supply voltage to detect all full open defects. Experiments on synthesised benchmarks using an extended version of the fault simulator tool mentioned above, measure the quantitative impact of supply voltage variation on defect coverage.The final part studies the impact of process variation on the behaviour of bridge defects. Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation

NASA Space Engineering Research Center for VLSI systems design

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Detection of hard faults in combinational logic circuits

ABSTRACT: Previous Work in identifying hard to test faults (HFs) -- The effect of reconvergent fanout and redundancy -- Testability measures (TMs)Using of ATPGs to detect HFs -- Previous use of cost in Testability analysis -- Review of automatic test pattern generation (ATPG) -- Fault modelling -- Single versus multiple path sensitization -- The four ATPG phases of deterministic gate level test generation -- Random test pattern generation and hybrid methods -- Review of the fan algorithm -- Backtrack reduction methods and the importance of heuristics -- Mixed graph -- binary decision diagram (GBDD) circuit model -- A review of graph techniques -- A review of binary decisions diagrams (BDDs) techniques -- gBDD -- graph binary decision diagrams -- Detection of hard faults using HUB -- Introduction to budgetary constraints -- The HUB algorithm -- Important HUB attributes -- Circuits characteristics of used for results -- Comparison of gBDD -- ATPG related results -- Fault simulation related results -- Hard fault detection

Conception pour la testabilité des systèmes biomédicaux implantables

Architecture générale des systèmes implantables -- Principes de stimulation électrique -- Champs d'application des systèmes implantables -- Les particularités des circuits implantables -- Tendance future -- Conception pour la testabilité de la partie numérique des circuits implantables -- "Desigh and realization of an accurate built-in current sensor for Iddq testing and power dissipation measurement -- Conception pour la testabilité de la partie analogique des circuits implantables -- BIST for digital-to-analog and Analogo-to-digital converters -- Efficient and accurate testing of analog-to-digital converters using oscillation test method -- Design for testability of Embedded integrated operational amplifiers -- Vérification des interfaces bioélectroniques des systèmes implantables -- Monitorin the electrode and lead failures in implanted microstimulators and sensors -- Capteurs de température intégrés pour la vérification de l'état thermique des puces dédiées -- Built-in temperature sensors for on-line thermal monitoring of microelectronic structures -- Un protocole de communication fiable pour la programmation et la télémétrie des système implantables -- A reliable communication protoco for externally controlled biomedical implanted devices

The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design

Generating Circuit Tests by Exploiting Designed Behavior

This thesis describes two programs for generating tests for digital circuits that exploit several kinds of expert knowledge not used by previous approaches. First, many test generation problems can be solved efficiently using operation relations, a novel representation of circuit behavior that connects internal component operations with directly executable circuit operations. Operation relations can be computed efficiently by searching traces of simulated circuit behavior. Second, experts write test programs rather than test vectors because programs are more readable and compact. Test programs can be constructed automatically by merging program fragments using expert-supplied goal-refinement rules and domain-independent planning techniques

NASA Tech Briefs, Spring 1977

Topics: NASA TU Services: Technology Utilization services that can assist you in learning about and applying NASA technology; New Product Ideas: A summary of sel~ted innovations of value to manufacturers for the development of new products; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Life Sciences; Mechanics; Machinery; Fabrication Technology; Mathematics and Information Sciences