266 research outputs found
A HIGH PERFORMANCE FULLY DIFFERENTIAL PURE CURRENT MODE OPERATIONAL AMPLIFIER AND ITS APPLICATIONS
In this paper a novel high performance all current-mode fully-differential (FD) Current mode Operational Amplifier (COA) in BIPOLAR technology is presented. The unique true current mode simple structure grants the proposed COA the largest yet reported unity gain frequency while providing low voltage low power operation. Benefiting from some novel ideas, it also exhibits high gain, high common mode rejection ratio (CMRR), high power supply rejection ratio (PSRR), high output impedance, low input impedance and most importantly high current drive capability. Its most important parameters are derived and its performance is proved by PSPICE simulations using 0.8 μm BICMOS process parameters at supply voltage of ±1.2V indicating the values of 82.4 dB,52.3º, 31.5 Ω, 31.78 MΩ, 179.2 dB, 2 mW and 698 MHz for gain, phase margin, input impedance, output impedance, CMRR, power and unity gain frequency respectively. Its CMRR also shows very high frequency of 2.64 GHz at zero dB. Its very high PSRR+/PSRR- of 182 dB/196 dB makes the proposed COA a highly suitable block in Mixed-Mode (SOC) chips. Most favourably it can deliver up to ±1.5 mA yielding a high current drive capability exceeding 25. To demonstrate the performance of the proposed COA, it is used to realize a constant bandwidth voltage amplifier and a high performance Rm amplifier
A 0.3 V rail-to-rail ultra-low-power OTA with improved bandwidth and slew rate
In this paper, we present a novel operational transconductance amplifier (OTA) topology
based on a dual-path body-driven input stage that exploits a body-driven current mirror-active
load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or
biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore
be compensated at the output stage, thus not requiring Miller compensation. The input stage
ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both
a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an
STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it
achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive
PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the
robustness of the proposed amplifier
Novel approaches in current-feedback operational amplifier design
The aim of this research programme was to design and develop a novel bipolar
junction transistor Current Feedback Operational Amplifier (CFOA) with a good
Common-Mode Rejection Ratio (CMRR), suitable for radio frequency (RF)
applications. This research focused on investigation of the established CFOA with
the emphases of improving CMRR, bandwidth, Voltage-Offset and Slew-rate
performance. The majority of the results of this work have been reported by the
author in references [11 to [6].
Initially a thorough analysis of the conventional CFOA was undertaken to provide an
in depth understanding of the amplifier's operation, and this work revealed that the
main shortcomings of the CFOA are in the design of the input stage. This initial
study focussed on establishing reasons for the poor DC offset-voltage performance
and CMRR and confirmed that these designs have inherently poor performance in
these two elements. The analysis was carried out using both theoretical modelling
and computer simulation.
Using this analysis of the conventional CFOA as a benchmark, various novel circuit
techniques were investigated. Several new input circuits for the CFOA were
proposed with respect to improving the three previously mentioned key
characteristics, viz., CMRR, offset voltage, and slew-rate. The first technique
explored is based on floating the entire input stage of the CFOA which yielded
significant improvements in CMRR, Offset-Voltage and bandwidth, and the results of
this workwere published in [11, [2], and P). Based on these initial findings a second
major development was undertaken. This time a bootstrapping technique was
employed to key sections of the input stage, leading to new, simplified input circuit
topology. This development leads to low DC offset voltage, wide bandwidth and high
CNIRR, as well as improved gain accuracy, and was published by the author in [4,5].
A logical approach to the different input stage architectures examined by the author
resulted in identification of a hierarchy of 6 different input CFOA circuit designs and
a comparative study was undertaken showing their relative performance in respect of
CMRR, Offset-Voltage and Slew-rate. This work was presented by the author, [6]
Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.
In the context of nowadays CMOS technology downscaling and the increasing demand of high performance electronics by industry and consumers, analog design has become a major challenge.
On the one hand, beyond others, amplifiers have traditionally been a key cell for many analog systems whose overall performance strongly depends on those of the amplifier. Consequently, still today, achieving high performance amplifiers is essential. On the other hand, due to the increasing difficulty in achieving high performance amplifiers in downscaled modern technologies, a different research line that replaces the amplifier by other more easily achievable cells appears: the so called amplifier-less techniques.
This thesis explores and contributes to both philosophies. Specifically, a lowvoltage differential input pair is proposed, with which three multistage amplifiers in the state of art are designed, analysed and tested. Moreover, a structure for the implementation of differential switched capacitor circuits, specially suitable for comparator-based circuits, that features lower distortion and less noise than the classical differential structures is proposed, an, as a proof of concept, implemented in a ΔΣ modulator
A 0.3 V, rail-to-rail, ultralow-power, non-tailed, body-driven, sub-threshold amplifier
A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is
proposed in this paper. The input stage exploits a replica bias control loop to set the common mode
current and a common mode feed-forward strategy to set its output common mode voltage. This
novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered
operational amplifier. A dual path compensation strategy is exploited to improve the frequency
response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology
from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power
consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around
3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of
60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state
of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and
Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and
mismatch variations
An ultra-low-voltage class-AB OTA exploiting local CMFB and body-to-gate interface
In this work a novel bulk-driven (BD) ultra-low-voltage (ULV) class-AB operational transconductance amplifier (OTA) which exploits local common mode feedback (LCMFB) strategies to enhance performance and robustness against process, voltage and temperature (PVT) variations has been proposed. The amplifier exploits body-to-gate (B2G) interface to increase the slew rate and attain class-AB behaviour, whereas two pseudo-resistors have been employed to increase the common mode rejection ratio (CMRR). The architecture has been extensively tested through Monte Carlo and PVT simulations, results show that the amplifier is very robust in terms of gain-bandwidth-product (GBW), power consumption and slew rate. A wide comparison against state-of-the-art has pointed out that best small-signal figures of merit are attained and good large-signal performance is guaranteed, also when worst-case slew rate is considered
Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors
The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 µW. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 µm TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit
An electrocardiogram readout circuit based on CMOS operational floating current conveyor
Electrocardiogram (ECG) is used in diagnosing heart diseases. It is designed as integration between current-mode instrumentation amplifiers (CMIA) and low pass filter (LPF). Normal heart behavior can be identified simply by normal ECG that consists of signal while heart disorder can be recognized by having differences in the features of their corresponding ECG waveform. A novel integrated CMOS-based operational floating current conveyor (OFCC) circuit is proposed. OFCC is a five port general purpose analog building block which combines all the features of different current mode devices such as the second generation current conveyor (CCII), the current feedback operational amplifier (CFA), and the operational floating conveyor (OFC). The OFFC is modeled and simulated using UMC 130nm CMOS technology kit in Cadence with a supply voltage 1.2V. The ECG readout circuit has been designed using the proposed OFCC as a building block. The advantages of this: it is integrated, noise factor is small as the proposed OFCC has the lowest input noise voltage and the layout is simple as it is a single block that can be repeated several times
- …