An analog building block for signal conditioning instrumentation circuits

The design of analog signal conditioning circuits for instrumentation applications often requires designing a specific circuit for each case. For board-level design solutions, these circuits are generally implemented by using Operational Amplifiers (OA) and Instrumentation Amplifiers (IA). An analog building block (ABB) is proposed, which can be implemented with three standard OAs. Using different connection schemes and just adding a few resistors, it allows implementing several analog circuits such as common-mode conditioners, single-ended to differential and differential to single-ended converters, voltage and current amplifiers, current-to-voltage and voltage-to-current converters, among others. The proposed ABB is analyzed and applied to several typical analog conditioning problems. The design equations and experimental results for these circuits are presented.Fil: Spinelli, Enrique Mario. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; ArgentinaFil: Haberman, Marcelo Alejandro. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentin

An electrocardiogram readout circuit based on CMOS operational floating current conveyor

Electrocardiogram (ECG) is used in diagnosing heart diseases. It is designed as integration between current-mode instrumentation amplifiers (CMIA) and low pass filter (LPF). Normal heart behavior can be identified simply by normal ECG that consists of signal while heart disorder can be recognized by having differences in the features of their corresponding ECG waveform. A novel integrated CMOS-based operational floating current conveyor (OFCC) circuit is proposed. OFCC is a five port general purpose analog building block which combines all the features of different current mode devices such as the second generation current conveyor (CCII), the current feedback operational amplifier (CFA), and the operational floating conveyor (OFC). The OFFC is modeled and simulated using UMC 130nm CMOS technology kit in Cadence with a supply voltage 1.2V. The ECG readout circuit has been designed using the proposed OFCC as a building block. The advantages of this: it is integrated, noise factor is small as the proposed OFCC has the lowest input noise voltage and the layout is simple as it is a single block that can be repeated several times

A Novel Fully Differential Second Generation Current Conveyor and Its Application as a Very High CMRR Instrumentation Amplifier

This paper aims to introduce a novel Fully Differential second generation Current Conveyor (FDCCII) and its application to design a novel Low Power (LP), very high CMRR, and wide bandwidth (BW) Current Mode Instrumentation Amplifier (CMIA). In the proposed application, CMRR, as the most important feature, has been greatly improved by using both common mode feed forward (CMFF) and common mode feedback (CMFB) techniques, which are verified by a perfect circuit analysis. As another unique quality, it neither needs well-matched active blocks nor matched resistors but inherently improves CMRR, BW, and power consumption hence gains an excellent matchless choice for integration. The FDCCII has been designed using 0.18 um TSMC CMOS Technology with ±1.2 V supply voltages. The simulation of the proposed FDCCII and CMIA have been done in HSPICE LEVEL 49. Simulation results for the proposed CMIA are as follow: Voltage CMRR of 216 dB, voltage CMRR BW of 300 Hz. Intrinsic resistance of X-terminals is only 45 Ω and the power dissipation is 383.4 μW.  Most favourably, it shows a constant differential voltage gain BW of 18.1 MHz for variable gains (here ranging from 0 dB to 45.7 dB for example) removing the bottleneck of constant gain-BW product of Voltage mode circuits

Design of the fully differential operational floating conveyor and its applications

Analog circuits can be generally classified into two broad categories: The first one includes analog circuits operating in the voltage mode, while the second category includes those operating in the current mode. Voltage mode analog circuit’s bandwidth is highly dependent on the gain via the gain bandwidth product (GBP). To solve this problem, many current mode circuits are developed such as the second generation Current Conveyor (CCII) and the Operational Floating Conveyor (OFC). A novel concept of the Fully Differential Operational Floating Conveyor (FD-OFC) is presented for the first time, to the best of the author’s knowledge. A CMOS design for the proposed FD-OFC is introduced as an 8 (4x4) port general purpose analog building block. The FD-OFC design is implemented using two different realizations. The proposed design has the advantage of low power consumption as it operates under biasing conditions of only 1.2 V while its wide bandwidth reaches 600 MHz. These operating conditions recommend the proposed device to be integrated to a wide range of low power-wide high speed applications. The terminal behavior of the proposed device is mathematically modeled and its operation is simulated using the UMC 130 nm technology kit in Cadence environment. Differential voltage amplifier, current mode instrumentation amplifier (CMIA) and Fully Differential second generation Current Conveyor (FDCCII) are examples of the presented applications based on the proposed FD-OFC

A New Proposal for OFCC-based Instrumentation Amplifier

This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values of resistors.  The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included

Re-design of Precision Signal Conditioning Circuit for detecting Schumann Resonance

Extremely low frequencies signals are waves between 3 to 30Hz and corresponding wavelengths between 10,000 to 100,000 kilometers. The specific signals used here are generated from lightning and are excited at frequencies around 8Hz, 14Hz, 20Hz. These are often called Schumann Resonance frequencies. Several stations have been built around the world for identifying ELF waves. All of those required a sparsely populated area that was far away from electric power lines because of interference from electric noise at 50 Hz and 60Hz. This project develops and tests an amplifier and filter circuit that should assist in identifying the Schumann Resonance signals in more electrically noisy environments. Detecting these extremely small signals requires circuits which have low internal noise among other characteristics. Analog Devices has recently produced a Precision Signal Conditioning Integrated Circuit (the AD8421) which has very low internal noise. The work reported herein uses Analog Devices\u27 new chip and amplifies these very low voltages and then actively filters electric noise at these low frequencies using the AD8510. A Printed Circuit Board (PCB) was designed to help shield the circuit from the interference of higher frequencies in the surrounding environment. This design detects input voltages below 5 micro volts and gives a significantly amplified output. Voltage vs frequency and input vs output voltage characteristics are plotted for this design

Noise Figure Measurement of Differential Amplifiers Using non-Ideal Baluns

This paper analyzes the noise and gain measurement of microwave differential amplifiers using two passive baluns. A general model of the baluns is considered, including potential losses and phase/amplitude unbalances. This analysis allows de-embedding the actual gain and noise performance of the isolated amplifier by using single-ended measurements of the cascaded system and baluns. Finally, measured results from two amplifier prototypes are used to validate the theoretical principles

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces