Remote Cell Growth Sensing Using Self-Sustained Bio-Oscillations

A smart sensor system for cell culture real-time supervision is proposed, allowing for a significant reduction in human effort applied to this type of assay. The approach converts the cell culture under test into a suitable “biological” oscillator. The system enables the remote acquisition and management of the “biological” oscillation signals through a secure web interface. The indirectly observed biological properties are cell growth and cell number, which are straightforwardly related to the measured bio-oscillation signal parameters, i.e., frequency and amplitude. The sensor extracts the information without complex circuitry for acquisition and measurement, taking advantage of the microcontroller features. A discrete prototype for sensing and remote monitoring is presented along with the experimental results obtained from the performed measurements, achieving the expected performance and outcomes

Application of LSI to signal detection: The deltic DFPCC

The development of the DELTIC DFPCC serial mode signal processor is discussed. The processor is designed to detect in the presence of background noise a signal coded into the zero crossings of the waveform. The unique features of the DELTIC DFPCC include versatility in handling a variety of signals and relative simplicity in implementation. A theoretical performance model is presented which predicts the expected value of the output signal as a function of the input signal to noise ratio. Experimental results obtained with the prototype system, which was breadboarded with LSI, MSI and SSI components, are given. The device was compared with other LSI schemes for signal processing and it was concluded that the DELTIC DFPCC is simpler and in some cases more versatile than other systems. With established LSI technology, low frequency systems applicable to sonar and similar problems are feasible

Dynamic element matching techniques for data converters

Analog to digital converter (ADC) circuit component errors create nonuniform quantization code widths and create harmonic distortion in an ADC\u27s output. In this dissertation, two techniques for estimating an ADC\u27s output spectrum from the ADC\u27s transfer function are determined. These methods are compared to a symmetric power function and asymmetric power function approximations. Standard ADC performance metrics, such as SDR, SNDR, SNR, and SFDR, are also determined as a function of the ADC\u27s transfer function approximations. New dynamic element matching (DEM) flash ADCs are developed. An analysis of these DEM flash ADCs is developed and shows that these DEM algorithms improve an ADC\u27s performance. The analysis is also used to analyze several existing DEM ADC architectures; Digital to analog converter (DAC) circuit component errors create nonuniform quantization code widths and create harmonic distortion in a DAC\u27s output. In this dissertation, an exact relationship between a DAC\u27s integral nonlinearity (INL) and its output spectrum is determined. Using this relationship, standard DAC performance metrics, such as SDR, SNDR, SNR, and SFDR, are calculated from the DAC\u27s transfer function. Furthermore, an iterative method is developed which determines an arbitrary DAC\u27s transfer function from observed output magnitude spectra. An analysis of DEM techniques for DACs, including the determination of several suitable metrics by which DEM techniques can be compared, is derived. The performance of a given DEM technique is related to standard DAC performance metrics, such as SDR, SNDR, and SFDR. Conditions under which DEM techniques can guarantee zero average INL and render the distortion due to mismatched components as white noise are developed. Several DEM circuits proposed in the literature are shown to be equivalent and have hardware efficient implementations based on multistage interconnection networks. Example DEM circuit topologies and their hardware efficient VLSI implementations are also presented

Analysis and design of high-transconductance RF mosfet voltage to-current converters

The research described in this thesis is concerned with analysis and design of "HighTransconductance RF MOSFET Voltage-to-Current (V-I) Converters". Various V-I converter circuits published in the past have been reviewed by the author in order to understand the different techniques employed to improve transconductance (Gt), linear operating range and total harmonic distortion (THO). Throughout this research, the emphasis has been to improve the above mentioned parameters. All the V-I converter circuits reported have been simulated using PSPICE and the results compared with the values obtained by theoretical analysis. Some of the results of this work have been already reported by the author in the technical literature. (See Chapter 9, at the end of this thesis, where reference to two publications by the author is given.) It was essential to obtain accurate CMOS device parameters values, such as Early Voltage, transconductance parameter ratios!! (gm/gds), X (gmbl'gm) and inter-electrode capacitances, to facilitate the design the prQcess. This was achieved using an extensive set of simulations for the transistor operating under different bias conditions. Furthermore, a measurement technique, thought to be novel, for the direct determination of the transconductance ratios!! and X is proposed. In the next part of the work several types of current mirror are compared against the standard current mirrors, using analytical and simulation methods. Furthermore several MOSFET V-I converter designs were critically reviewed to understand the various existing techniques and their limitations. Two novel techniques, Drain-Source Feedback Circuits (DSFCs) and Drain-Gate Feedback Circuits (OGFCs) ere implemented with a new temperature-compensation scheme, designed to operate well in an industrial environment (-40°C - +8S°C). It is found that the best types of V -I converters were the DSFCs which, offer a more accurate value of Gt (3.386mS) and the THO less than -S7dB for a differential input operating range SOOm V at 1 GHz with a 3V total rail voltage. The OGFC circuits were also meet the initial design targets, the value of THO is less then -SOdB, and operating in the Giga hertz frequency range is possible. Preliminary investigation on future work shows promising results

Design of a High-Performance High-Pass Generalized Integrator Based Single-Phase PLL

Grid-interactive power converters are normally synchronized to the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations and dc offsets in single-phase systems. In this paper, a single-phase PLL is presented to mitigate the effects of these non-idealities. This PLL is based on the popular second order generalized integrator (SOGI) structure. The SOGI structure is modified to eliminate of the effects of input dc offsets. The resulting SOGI structure has a high-pass filtering property. Hence, this PLL is termed as high-pass generalized integrator based PLL (HGI-PLL). It has fixed parameters which reduces the implementation complexity and aids in the implementation in low-end digital controllers. The HGI-PLL is shown to have least resource utilization among the SOGI based PLLs with dc cancelling capability. Systematic design methods are evolved leading to the design that limits the unit vector THD to within 1% for given non-ideal input conditions in terms of frequency deviation and harmonic distortion. The proposed designs achieve the fastest transient response. The performance of this PLL has been verified experimentally. The results are found to agree with the theoretical prediction.Comment: 22 pages, 13 figures and 2 table

Stochastic macromodeling of nonlinear systems via polynomial chaos expansion and transfer function trajectories

A novel approach is presented to perform stochastic variability analysis of nonlinear systems. The versatility of the method makes it suitable for the analysis of complex nonlinear electronic systems. The proposed technique is a variation-aware extension of the Transfer Function Trajectory method by means of the Polynomial Chaos expansion. The accuracy with respect to the classical Monte Carlo analysis is verified by means of a relevant numerical example showing a simulation speedup of 1777 X

Development of a High-Efficiency, Low-Power RF Power Amplifier for Use in a High-Temperature Environment

This thesis presents a study of the design of a high efficiency, low power, RF power amplifier that can operate over an extended temperature range. The amplifier has been implemented as a hybrid circuit with the active device fabricated in a 0.5μm silicon-on- sapphire CMOS technology and passive components implemented off-chip. First a review of power amplifiers is given. Next design considerations for low power, high efficiency amplifiers are presented. Finally design details and measurement results from a low-power Class E amplifier are presented. When operated with an output power of 1 mW, the Class E amplifier achieves an efficiency greater than 40% over the frequency band 250 MHz to 310 MHz at 25 C and from 265 MHz to 295 MHz at 200 C

CMOS OTA-C high-frequency sinusoidal oscillators

Several topology families are given to implement practical CMOS sinusoidal oscillators by using operational transconductance amplifier-capacitor (OTA-C) techniques. Design techniques are proposed taking into account the CMOS OTA's dominant nonidealities. Building blocks are presented for amplitude control, both by automatic gain control (AGC) schemes and by limitation schemes. Experimental results from 3- and 2- mu m CMOS (MOSIS) prototypes that exhibit oscillation frequencies of up to 69 MHz are obtained. The amplitudes can be adjusted between 1 V peak to peak and 100 mV peak to peak. Total harmonic distortions from 2.8% down to 0.2% have been measured experimentally.Comisión Interministerial de Ciencia y Tecnología ME87-000