High-Level Synthesis of Digital Circuits

Táto práca sa zaoberá praktickým otestovaním behaviorálnej syntézy ako spôsobu návrhu digitálnych obvodov a jej momentálnym progresom pri tvorbe RTL popisov. V úvode práce sú popísané hlavné úlohy behaviorálnej syntézy spolu s knižnicou tried jazyka C++ nazvanou SystemC, ktorá implementuje hardvérové konštrukcie, dátové typy s definovateľnou dátovou šírkou a vie pracovať s časom. Ďalej sa práca zameriava na diskrétnu Fourierovu transformáciu a jej modifikáciu pre efektívnejší výpočet – rýchlu Fourierovu transformáciu. V praktickej časti práce je navrhnutý referenčný model algoritmu FFT, ktorý je ďalej vhodne upravený a prevedený nástrojom pre behaviorálnu syntézu Stratus High-Level Synthesis do viacerých hardvérových architektúr.This thesis deals with practical test of high-level synthesis as a digital circuits design method and its current progress in creating RTL models. At first main tasks of HLS will be described together with C++ library of classes called SystemC, which implements hardware constructs, notion of time and hardware datatypes with arbitrary bit width. After that thesis focuses on discrete Fourier transform and its fast form of computation – fast Fourier transform. In the practical part of thesis reference FFT model is written in C++ language, which is later edited appropriately a synthesized with Stratus High-Level Synthesis tool into several hardware architectures.

Incorporating VHDL signal/wait semantics into synthesis

VHDL signals and wait statements provide great expressive power for behavioral descriptions. However, due to their simulation semantics, most high-level synthesis tools do not handle these constructs and severely restrict their use, eliminating much of their power. In this report, we introduce a set of transformations to convert signals and wait statements to equivalent constructs that are easily handled by high-level synthesis tools. They greatly enlarge the synthesizable VHDL subset, thus increasing the usefulness and practicality of the language as an input to high-level synthesis. These transformations can also serve as a basis for converting a VHDL process to a form suitable for generation of software

Automated Synthesis of SEU Tolerant Architectures from OO Descriptions

SEU faults are a well-known problem in aerospace environment but recently their relevance grew up also at ground level in commodity applications coupled, in this frame, with strong economic constraints in terms of costs reduction. On the other hand, latest hardware description languages and synthesis tools allow reducing the boundary between software and hardware domains making the high-level descriptions of hardware components very similar to software programs. Moving from these considerations, the present paper analyses the possibility of reusing Software Implemented Hardware Fault Tolerance (SIHFT) techniques, typically exploited in micro-processor based systems, to design SEU tolerant architectures. The main characteristics of SIHFT techniques have been examined as well as how they have to be modified to be compatible with the synthesis flow. A complete environment is provided to automate the design instrumentation using the proposed techniques, and to perform fault injection experiments both at behavioural and gate level. Preliminary results presented in this paper show the effectiveness of the approach in terms of reliability improvement and reduced design effort

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

VSS : a VHDL synthesis system

This report describes a register transfer synthesis system that allows a designer to interact with the design process. The designer can modify the compiled design by changing the input description, selecting optimization and mapping strategies, or graphically changing the generated design schematic. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization. The compilation process consists of two phases. First, a design composed of generic components is synthesized from the input description. Second, this design is translated into components from a particular library by a mapper and optimized by a logic optimizer. Redesign to new technologies can be accomplished by changing only the component library

An empirical evaluation of High-Level Synthesis languages and tools for database acceleration

High Level Synthesis (HLS) languages and tools are emerging as the most promising technique to make FPGAs more accessible to software developers. Nevertheless, picking the most suitable HLS for a certain class of algorithms depends on requirements such as area and throughput, as well as on programmer experience. In this paper, we explore the different trade-offs present when using a representative set of HLS tools in the context of Database Management Systems (DBMS) acceleration. More specifically, we conduct an empirical analysis of four representative frameworks (Bluespec SystemVerilog, Altera OpenCL, LegUp and Chisel) that we utilize to accelerate commonly-used database algorithms such as sorting, the median operator, and hash joins. Through our implementation experience and empirical results for database acceleration, we conclude that the selection of the most suitable HLS depends on a set of orthogonal characteristics, which we highlight for each HLS framework.Peer ReviewedPostprint (author’s final draft

Structured modeling for VHDL synthesis

This report will describe a proposed modeling style for the use of the VHSIC Hardware Description Language (VHDL) in design synthesis. We will describe the operations and underlying assumptions of four design models currently understood and used in practice by designers: combinational logic, functional descriptions (involving clocked components such as counters), register transfer (data path) descriptions, and behavioral (instruction set or processor) designs. We will illustrate the various uses of the VHDL description styles (structural, dataflow and behavioral) to represent characteristics of each of these design models. Emphasis is placed on how VHDL constructs should be used in order to synthesize optimal designs

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing

LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC.Peer ReviewedPostprint (author's final draft