Exploiting partial reconfiguration through PCIe for a microphone array network emulator

The current Microelectromechanical Systems (MEMS) technology enables the deployment of relatively low-cost wireless sensor networks composed of MEMS microphone arrays for accurate sound source localization. However, the evaluation and the selection of the most accurate and power-efficient network’s topology are not trivial when considering dynamic MEMS microphone arrays. Although software simulators are usually considered, they consist of high-computational intensive tasks, which require hours to days to be completed. In this paper, we present an FPGA-based platform to emulate a network of microphone arrays. Our platform provides a controlled simulated acoustic environment, able to evaluate the impact of different network configurations such as the number of microphones per array, the network’s topology, or the used detection method. Data fusion techniques, combining the data collected by each node, are used in this platform. The platform is designed to exploit the FPGA’s partial reconfiguration feature to increase the flexibility of the network emulator as well as to increase performance thanks to the use of the PCI-express high-bandwidth interface. On the one hand, the network emulator presents a higher flexibility by partially reconfiguring the nodes’ architecture in runtime. On the other hand, a set of strategies and heuristics to properly use partial reconfiguration allows the acceleration of the emulation by exploiting the execution parallelism. Several experiments are presented to demonstrate some of the capabilities of our platform and the benefits of using partial reconfiguration

Dynamic Recofiguration Techniques for Wireless Sensor Networks

The need to achieve extended service life by battery powered Wireless Sensor Networks (WSNs) requires new concepts and technqiues beyond the state-of-the-art low-power designs based on fixed hardware platforms or energy-efficient protocols. This thesis investigates reconfiguration techniques that enable sensor hardware to adapt its energy consumption to external dynamics, by means of Dynamic Voltage Scaling (DVS), Dynamic Modulation Scaling (DMS), and other related concepts. For sensor node-level reconfiguration, an integration of DVS and DMS techniques was proposed to minimize the total energy consumption. A dynamic time allocation algorithm was developed, demonstrating an average of 55% energy reduction. For network-level reconfiguration, a node activation technique was presented to reduce the cost of recharging energy-depleted sensor nodes. Network operation combined with node activation was modeled as a stochastic decision process, where the activation decisions directly affected the energy efficiency of the network. An experimental test bed based on the Imote2 sensor node platform was realized, which demonstrated energy reduction of up to 50%. Such energy saving can be effectively translated into prolonged service life of the sensor network

Design Concept of Dynamic-Adaptive Reconfigurable Wireless Sensor Node (DARWiSeN)

This paper describe the proposed design concept of wireless sensor node named Dynamic-Adaptive Reconfigurable Wireless Sensor Node (DARWiSeN), with special emphasis on the design principles and functionality. The design concept is targeted to a wireless sensor node prototype that has ability to adapt various applications and situation with a minimal redesign effort through concept of reconfigurable hardware and modularity approach. Both the hardware and software components are detailed, together with experimental evaluation. The experimental evaluation revealed that this approach is not only capable to show rapid prototype of wireless sensor application design, but it can also be used as a generic wireless node platform design in dynamic-adaptive reconfigurable feature, flexible, and greatly extending its applicability

Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks

While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements

Embedded Reconfigurable Techniques in Wireless Sensor Network Applications

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Architectures for Wireless Sensor Networks

Various architectures have been developed for wireless sensor networks. Many of them leave to the programmer important concepts as the way in which the inter-task communication and dynamic reconfigurations are addressed. In this paper we describe the characteristics of a new architecture we proposed - the data-centric architecture. This architecture offers an easy way of structuring the applications designed for wireless sensor nodes that confers them superior performances