505 research outputs found
Bibliometric Review of NoC Router Optimization
Network on chip (NoC) has been proposed as an emerging solution for scalability and performance demands of next generation System on Chip (SoC). NoC provides a solution for the bus based interconnection issue of SoC, where large numbers of Intellectual Property modules (IP) are integrated on a single chip for better performance. The NoC has several advantages such as scalability, low latency and low power consumption, high bandwidth over dedicated wires and buses. Interconnections between multiple chip cores have a significant impact on the communication and performance of the chip design in terms of region, latency, throughput and power. In the NoC architecture, the router is a dominant component that significantly affects the performance of the NoC. NoC router architectures evolved since the year 2002 and progress in the domain pertaining to the optimization in the NoC router architectures has been discussed. The key objective of this bibliometric review is to understand the extent of the existing literature in the domain of performance efficient NoC router architectures. The bibliometric analysis is primarily based on data extracted from Scopus. It reveals that major contributions are done by researchers from USA, China followed by India in the form of conference, journals and articles publications. The major contribution is by the subject areas of Computer Science and Engineering followed by Mathematics and Material Science. The geographical analysis is done by using the GPS visualize tool. The clusters were created using Gephi
Communication centric platforms for future high data intensive applications
The notion of platform based design is considered as a viable solution to boost the
design productivity by favouring reuse design methodology. With the scaling down of
device feature size and scaling up of design complexity, throughput limitations, signal
integrity and signal latency are becoming a bottleneck in future communication centric
System-on-Chip (SoC) design. This has given birth to communication centric platform
based designs.
Development of heterogeneous multi-core architectures has caused the on-chip
communication medium tailored for a specific application domain to deal with multidomain
traffic patterns. This makes the current application specific communication centric
platforms unsuitable for future SoC architectures.
The work presented in this thesis, endeavours to explore the current
communication media to establish the expectations from future on-chip interconnects. A
novel communication centric platform based design flow is proposed, which consists of
four communication centric platforms that are based on shared global bus, hierarchical
bus, crossbars and a novel hybrid communication medium. Developed with a smart
platform controller, the platforms support Open Core Protocol (OCP) socket standard,
allowing cores to integrate in a plug and play fashion without the need to reprogram the
pre-verified platforms. This drastically reduces the design time of SoC architectures. Each
communication centric platform has different throughput, area and power characteristics,
thus, depending on the design constraints, processing cores can be integrated to the most
appropriate communication platform to realise the desired SoC architecture.
A novel hybrid communication medium is also developed in this thesis, which
combines the advantages of two different types of communication media in a single SoC
architecture. The hybrid communication medium consists of crossbar matrix and shared
bus medium . Simulation results and implementation of WiMAX receiver as a real-life
example shows a 65% increase in data throughput than shared bus based communication
medium, 13% decrease in area and 11% decrease in power than crossbar based
communication medium.
In order to automate the generation of SoC architectures with optimised
communication architectures, a tool called SOCCAD (SoC Communication architecture
development) is developed. Components needed for the realisation of the given application
can be selected from the tool’s in-built library. Offering an optimised communication
centric placement, the tool generates the complete SystemC code for the system with
different interconnect architectures, along with its power and area characteristics. The
generated SystemC code can be used for quick simulation and coupled with efficient test
benches can be used for quick verification.
Network-on-Chip (NoC) is considered as a solution to the communication
bottleneck in future SoC architectures with data throughput requirements of over 10GB/s.
It aims to provide low power, efficient link utilisation, reduced data contention and
reduced area on silicon. Current on-chip networks, developed with fixed architectural
parameters, do not utilise the available resources efficiently. To increase this efficiency, a
novel dynamically reconfigurable NoC (drNoC) is developed in this thesis. The proposed
drNoC reconfigures itself in terms of switching, routing and packet size with the changing
communication requirements of the system at run time, thus utilising the maximum
available channel bandwidth. In order to increase the applicability of drNoC, the network
interface is designed to support OCP socket standard. This makes drNoC a highly reuseable
communication framework, qualifying it as a communication centric platform for
high data intensive SoC architectures. Simulation results show a 32% increase in data
throughput and 22-35% decrease in network delay when compared with a traditional NoC
with fixed parameters
Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip
The sustained demand for faster, more powerful chips has been met by the
availability of chip manufacturing processes allowing for the integration of increasing
numbers of computation units onto a single die. The resulting outcome,
especially in the embedded domain, has often been called SYSTEM-ON-CHIP
(SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC).
MPSoC design brings to the foreground a large number of challenges, one of
the most prominent of which is the design of the chip interconnection. With a
number of on-chip blocks presently ranging in the tens, and quickly approaching
the hundreds, the novel issue of how to best provide on-chip communication
resources is clearly felt.
NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable
answer to this design concern. By bringing large-scale networking concepts to
the on-chip domain, they guarantee a structured answer to present and future
communication requirements. The point-to-point connection and packet switching
paradigms they involve are also of great help in minimizing wiring overhead
and physical routing issues. However, as with any technology of recent inception,
NoC design is still an evolving discipline. Several main areas of interest
require deep investigation for NoCs to become viable solutions:
• The design of the NoC architecture needs to strike the best tradeoff among
performance, features and the tight area and power constraints of the onchip
domain.
• Simulation and verification infrastructure must be put in place to explore,
validate and optimize the NoC performance.
• NoCs offer a huge design space, thanks to their extreme customizability in
terms of topology and architectural parameters. Design tools are needed
to prune this space and pick the best solutions.
• Even more so given their global, distributed nature, it is essential to evaluate
the physical implementation of NoCs to evaluate their suitability for
next-generation designs and their area and power costs.
This dissertation performs a design space exploration of network-on-chip architectures,
in order to point-out the trade-offs associated with the design of
each individual network building blocks and with the design of network topology
overall. The design space exploration is preceded by a comparative analysis
of state-of-the-art interconnect fabrics with themselves and with early networkon-
chip prototypes. The ultimate objective is to point out the key advantages
that NoC realizations provide with respect to state-of-the-art communication
infrastructures and to point out the challenges that lie ahead in order to make
this new interconnect technology come true. Among these latter, technologyrelated
challenges are emerging that call for dedicated design techniques at all
levels of the design hierarchy. In particular, leakage power dissipation, containment
of process variations and of their effects. The achievement of the above
objectives was enabled by means of a NoC simulation environment for cycleaccurate
modelling and simulation and by means of a back-end facility for the
study of NoC physical implementation effects. Overall, all the results provided
by this work have been validated on actual silicon layout
Network Interface Design for Network-on-Chip
In the culture of globalized integrated circuit (IC, a.k.a chip) production, the use of Intellectual Property (IP) cores, computer aided design tools (CAD) and testing services from un-trusted vendors are prevalent to reduce the time to market. Unfortunately, the globalized business model potentially creates opportunities for hardware tampering and modification from adversary, and this tampering is known as hardware Trojan (HT). Network-on-chip (NoC) has emerged as an efficient on-chip communication infrastructure. In this work, the security aspects of NoC network interface (NI), one of the most critical components in NoC will be investigated and presented. Particularly, the NI design, hardware attack models and countermeasures for NI in a NoC system are explored.
An OCP compatible NI is implemented in an IBM0.18ìm CMOS technology. The synthesis results are presented and compared with existing literature. Second, comprehensive hardware attack models targeted for NI are presented from system level to circuit level. The impact of hardware Trojans on NoC functionality and performance are evaluated. Finally, a countermeasure method is proposed to address the hardware attacks in NIs
Functional Testing Approaches for "BIFST-able" tlm_fifo
Evolution of Electronic System Level design methodologies, allows a wider use of Transaction-Level Modeling (TLM). TLM is a high-level approach to modeling digital systems that emphasizes on separating communications among modules from the details of functional units. This paper explores different functional testing approaches for the implementation of Built-in Functional Self Test facilities in the TLM primitive channel tlm_fifo. In particular, it focuses on three different test approaches based on a finite state machine model of tlm_fifo, functional fault models, and march tests respectivel
Performance Evaluation of XY and XTRANC Routing Algorithm for Network on Chip and Implementation using DART Simulator
In today’s world Network on Chip(NoC) is one of the most efficient on chip communication platform for System on Chip where a large amount of computational and storage blocks are integrated on a single chip. NoCs are scalable and have tackled the short commings of SoCs . In the first part of this project the basics of NoCs is explained which includes why we should use NoC , how to implement NoC ,various blocks of NoCs .The next part of the project deals with the implementation of XY routing algorithm in mesh (3*3) and mesh (4*4) network topologies. The throughput and latency curves for both the topologies were found and a through comparison was done by varying the no of virtual cannels. In the next part an improvised routing algorithm known as the extended torus(XTRANC) routing algorithm for NoCs implementation is explained. This algorithm is designed for inner torus mesh networks and provides better performance than usual routing algorithms. It has been implemented using the CONNECT simulator. Then the DART simulator was explored and two important components namely the flitqueue and the traffic generator was designed using this simulator
Design and Analysis of Router Architectures for NoC
The advance of process technology keeps on reducing the device size. As a result, the number of processing elements that can be integrated on a single chip (SoC) increases. The reduction in the device size also reducing the gate delay compared to the wire delay giving rise to increase in the frequency of operation of the devices. Further, in order to reduce the design time to market the communication system must support the plug and play architecture and should support design reuse. The conventional on-chip communication architecture, which consists of point-to-point connection and bus infrastructure, may not be able to provide sufficient communication requirements for SoC in terms of increasing the frequency of operation, providing reliability and flexibility. Further, conventional communication systems used for on-chip communication are not scalable and does not support design reuse. The NOC design represents a new paradigm to design multi-processor SoC which is scalable and supports design reuse. The NOC architecture uses layered protocols and packet switched networks which consist of on-chip routers, links and network interface on a predefined topology. NoC requires many on-chip resources which can increase the cost, area and power consumption. The efficiency of the NoC depends on how the resources are utilized for traversing the packet from source to destination which is determined by the flow control mechanism. The components which are used in the NoC for establishing communication between the modules of SoC were designed using VERILOG HDL. Different types of router architectures used by NoC were also designed mentioning their merits and demerits and their area and power consumption was also estimate
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