The notion of platform based design is considered as a viable solution to boost the
design productivity by favouring reuse design methodology. With the scaling down of
device feature size and scaling up of design complexity, throughput limitations, signal
integrity and signal latency are becoming a bottleneck in future communication centric
System-on-Chip (SoC) design. This has given birth to communication centric platform
based designs.
Development of heterogeneous multi-core architectures has caused the on-chip
communication medium tailored for a specific application domain to deal with multidomain
traffic patterns. This makes the current application specific communication centric
platforms unsuitable for future SoC architectures.
The work presented in this thesis, endeavours to explore the current
communication media to establish the expectations from future on-chip interconnects. A
novel communication centric platform based design flow is proposed, which consists of
four communication centric platforms that are based on shared global bus, hierarchical
bus, crossbars and a novel hybrid communication medium. Developed with a smart
platform controller, the platforms support Open Core Protocol (OCP) socket standard,
allowing cores to integrate in a plug and play fashion without the need to reprogram the
pre-verified platforms. This drastically reduces the design time of SoC architectures. Each
communication centric platform has different throughput, area and power characteristics,
thus, depending on the design constraints, processing cores can be integrated to the most
appropriate communication platform to realise the desired SoC architecture.
A novel hybrid communication medium is also developed in this thesis, which
combines the advantages of two different types of communication media in a single SoC
architecture. The hybrid communication medium consists of crossbar matrix and shared
bus medium . Simulation results and implementation of WiMAX receiver as a real-life
example shows a 65% increase in data throughput than shared bus based communication
medium, 13% decrease in area and 11% decrease in power than crossbar based
communication medium.
In order to automate the generation of SoC architectures with optimised
communication architectures, a tool called SOCCAD (SoC Communication architecture
development) is developed. Components needed for the realisation of the given application
can be selected from the tool’s in-built library. Offering an optimised communication
centric placement, the tool generates the complete SystemC code for the system with
different interconnect architectures, along with its power and area characteristics. The
generated SystemC code can be used for quick simulation and coupled with efficient test
benches can be used for quick verification.
Network-on-Chip (NoC) is considered as a solution to the communication
bottleneck in future SoC architectures with data throughput requirements of over 10GB/s.
It aims to provide low power, efficient link utilisation, reduced data contention and
reduced area on silicon. Current on-chip networks, developed with fixed architectural
parameters, do not utilise the available resources efficiently. To increase this efficiency, a
novel dynamically reconfigurable NoC (drNoC) is developed in this thesis. The proposed
drNoC reconfigures itself in terms of switching, routing and packet size with the changing
communication requirements of the system at run time, thus utilising the maximum
available channel bandwidth. In order to increase the applicability of drNoC, the network
interface is designed to support OCP socket standard. This makes drNoC a highly reuseable
communication framework, qualifying it as a communication centric platform for
high data intensive SoC architectures. Simulation results show a 32% increase in data
throughput and 22-35% decrease in network delay when compared with a traditional NoC
with fixed parameters
