Cross-border congestion management in the electricity market

EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Electrical resistivity as a measure of change of state in substrates: Design, development and validation of a microprocessor-based system.

Smart structures are relevant and significant because of their relevance to phenomena such as hazard mitigation, structural health monitoring and energy saving. Electrical resistance could potentially serve as an indicator of structural well-being or damage in the structure. To this end, the development of a microprocessor-based automated resistance measurement system with customized GUI is desired. In this research, a nodal electrical resistance acquisition circuit (NERAC) system was designed. The system hardware interfaces to a laptop, which houses a customized GUI developed using DAQFactory software. Resistance/impedance was measured using DC/AC methods with four-point probes technique, on three substrates. Baseline reading before damage was noted and compared with the resistance measured after damage. The device was calibrated and validated on three different substrates. Resistance measurements were taken from PVDF samples, composite panels and smart concrete. Results conformed to previous work done on these substrates, validating the effective working of the NERAC device

Analysis of surface mount technology solder joints

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.The factors determining the quality of surface mount technology (SMT) solder joints are numerous, and complex. The exploration of these factors, and how they may affect the reliability and quality of the joints can only be achieved through continuous research. In this project, essential areas of SMT joints were selected for study and analysis, with the intention of providing additional design and process guidelines for the production of quality SMT joints. In the infrared reflow process, one of the common defect phenomena is the occurrence of tombstoning; that is after soldering only one end of the component is soldered while the other is lifted up, assuming a position like a tombstone. The initiation of tombstoning during reflow was analysed based on the forces acting on the component. A model was developed to predict the initiation of this phenomenon. The model shows that, under vibration-free conditions, the surface tension of the molten solder is the source of the force causing the initiation of tombstoning. The contact angle, which varies with the length of the printed circuit board solder land, has a significant effect on the value of the surface tension acting as a force pulling upward on the component. The model further shows that tombstoning initiation is due to the combined effects of the surface tension; the weight of the component; the dimensions of the component; the length of the solder underneath the component; and the length of the solder protruding from the end of the component. Selected components were used as examples for predicting the conditions of initiation, and these conditions were further substantiated by a series of experiments. Another area of study was a method which directly pulled the components off printed circuit boards and this was used as a means for testing the bond quality of surface mount technology leadless chip solder joints. Components D7243, CC1206, RC1206, RC121O, and CC1 812 were selected for this study. It was found that the ultimate tensile force which breaks a component off the printed circuit board has the potential to be used as a parameter for measuring the quality of the solder joint. The effect of solder thickness on the strength of a joint has also been investigated. The shape of joints soldered by two methods, wave soldering and infrared reflow, were compared. Joints at the two ends of a component produced by infrared reflow were found more uniform than the ones produced by wave soldering. A recommendation is made here for the wave soldering approach in achieving uniform solder joints. The effects of solder shape on the joint strength were further investigated by finite element analysis. A convex joint was found marginally more robust than a concave joint. Two aspects of the internal structure of SMT solder joints were investigated, void content and copper/tin intermetallic compounds. The voiding conditions of wave-soldered and infrared reflow joints were compared. No voids were found in all specimens that were produced by wave soldering. However, there were always voids inside joints produced by infrared reflow. Microhardness tests indicated that the hardness of compounds at the copper/solder interface of infrared reflowed joints is lower than that in the wave-soldered joints. It is considered that the lower hardness of the interfacial region of the infrared reflowed joints is due to the presence of voids. Scanning electron microscopy was used to study the formation of copper/tin intermetallic compounds for joints produced by infrared reflow. The results show that Cu 6 Sn5 was the only compound with a detectable thickness. Other compounds such as Cu3 Sn, were virtually not found at all. Aging of the joints at 100°C, shows that both the Cu 6Sn5 and the overall interfacial thickness grew with time. One of the important areas which had been overlooked previously and was studied in some details was the effects of solder paste exposure on the quality of solder paste. The characteristic changes of solder paste due to exposure were investigated in three areas, weight loss, tackiness, and rheology. The evaporation of low boiling point solvents was considered as the main contribution to the loss in the weight of the solder paste. The weight loss against exposure time was found to follow an exponential behaviour. A method was designed to evaluate the tackiness changes of solder paste due to exposure. It was found that the decay of tackiness against exposure time can be expressed by a power law. It is recommended that solder paste manufacturers should provide the necessary characteristic constants so as to enable the characteristics to be calculated after a specific exposure. The rheological changes of the solder paste as a result of exposure were also investigated. The implication on the printability of the solder paste due to these changes was studied and discussed

Firefighting Remote Exploration Device II

The need for “smart” recovery for disasters is at the forefront. Firefighters operating in indoor firegrounds are put at risk by the constantly changing environment. The use of robotics in firefighting can assist firefighters by informing them about different aspects of the fireground, such as the structural layout and temperature distribution. Taking inspiration from a design devised by a previous WPI Major Qualifying Project, our team prototyped a heat, water, and impact-resistant robot capable of navigating around obstacles in the fireground and returning relevant real-time data

Compliant copper microwire arrays for reliable interconnections between large low-CTE packages and printed wiring board

The trend to high I/O density, performance and miniaturization at low cost is driving the industry towards shrinking interposer design rules, requiring a new set of packaging technologies. Low-CTE packages from silicon, glass and low-CTE organic substrates enable high interconnection density, high reliability and integration of system components. However, the large CTE mismatch between the package and the board presents reliability challenges for the board-level interconnections. Novel stress-relief structures that can meet reliability requirements along with electrical performance while meeting the cost constraints are needed to address these challenges. This thesis focuses on a comprehensive methodology starting with modeling, design, fabrication and characterization to validate such stress-relief structures. This study specifically explores SMT-compatible stress-relief microwire arrays in thin polymer carriers as a unique and low-cost solution for reliable board-level interconnections between large low-CTE packages and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled in between the interposer and printed wiring board (PWB) as stress-relief interlayers. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. The models were built in 2.5D geometries to study the reliability of 400 µm-pitch interconnections with a 100 µm thick, 20 mm × 20 mm silicon package that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared to that of ball grid array (BGA) interconnections, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of microwire arrays. Copper microwires with 12 µm diameter and 50 µm height were fabricated on both sides of a 50 µm thick, thermoplastic polymer carrier using dryfilm based photolithography and bottom-up electrolytic plating. The copper microwire interconnections were assembled between silicon interposer and FR-4 PWB through SMT-compatible process. Thermal mechanical reliability of the interconnections was characterized by thermal cycling test from -40°C to 125°C. The initial fatigue failure in the interconnections was identified at 700 cycles in the solder on the silicon package side, which is consistent with the modeling results. This study therefore demonstrated a highly-reliable and SMT-compatible solution for board-level interconnections between large low-CTE packages and printed wiring board.Ph.D

NASA Tech Briefs, February 1989

This issue contains a special feature on shaping the future with Ceramics. Other topics include: Electronic Components & and Circuits. Electronic Systems, Physical Sciences, Materials, Computer Programs, Mechanics, Machinery, Fabrication Technology, Mathematics and Information Sciences, and Life Sciences