Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology

With the recent advancements in semiconductor manufacturing towards smaller, faster and more efficient microelectronic systems, the problems of increasing leakage current and reduced breakdown voltage in bulk-CMOS transistors have become substantial in the sub-100-nanometer era. The Peregrine UltraCMOS Silicon-on-Sapphire (SOS) technology that uses highly-insulating sapphire substrate as insulator was introduced to meet the continually growing need for higher performance RF products. The electrically isolated circuit elements in the UltraCMOS technology lead to increased switching speeds and lower power consumption due to reduced junction and parasitic capacitances. Furthermore, the growing need for high-speed switching applications such as boosting a lower voltage level to a higher one gives the UltraCMOS technology an upper hand over the bulk-CMOS process. The limitation to using an UltraCMOS transistor is that its maximum drain to source voltage (VDS ) swing is 2.5V. This thesis aims to address this limitation by studying and implementing various stacking techniques in high power switching applications where voltage switching of higher than 2.5V are required. Fully-integrated DC to DC boost converters with switching circuits based on dynamically self-biased stacked transistors are proposed. For high voltage and high power handling, the proposed stacking techniques equally distribute the overall output voltage to less than 2.5V across each stacked transistor in the switch (V DS of 2.5V)

A High-Efficiency DC-DC Boost Converter for a Miniaturized Microbial Fuel Cell

Abstract-This paper presents a high-efficiency dc-dc boost converter to interface a miniaturized 50 μL microbial fuel cell (MFC) having 1 cm 2 vertically aligned carbon nanotube anode and 1 cm 2 Cr/Au cathode. Geobacteraceae-enriched mixed bacterial culture in growth medium and 100 mM buffered ferricyanide solutions are used as the anolyte and catholyte, respectively. The miniaturized MFC produces up to approximately 10 μW with an output voltage of 0.4-0.7 V. Such low voltage, which is also load dependent, prevents the MFC to directly drive low power electronics. A pulse-frequency modulation type dc-dc converter in discontinuous conduction mode is designed and implemented to address the challenges and provides a load independent output voltage with high conversion efficiency. The fabricated dc-dc converter in UMC 0.18 μm has been tested with the MFC. At 0.9 V output, the converter has a peak efficiency of 85% with 9 μW load

Reducing Power Loss, Cost and Complexity of SoC Power Delivery Using Integrated 3-Level Voltage Regulators

Traditional methods of system-on-chip (SoC) power management based on dynamic voltage and frequency scaling (DVFS) is limited by 1) cores/IP blocks sharing a voltage domain provided by off-chip voltage regulators (VR) and 2) slow voltage scaling time $(<0.1V/\mu s)$. This global, slow DVFS cannot track the increasingly heterogeneous, fluctuating performance requirements of individual microprocessor cores and SoC components. Furthermore, traditional off-chip VRs add significant area overhead and component cost on the board. This thesis explores replacing a large portion of existing off-chip VRs with integrated voltage regulators (IVR) that can scale the voltage at a 50 mV/ns rate, which is 500 times faster than microsecond-scale voltage scaling with existing off-chip VRs. IVRs occupy 10 times smaller footprint than off-chip VRs, making it easy to duplicate them to provide per-core or per-IP-block voltage control. This thesis starts by summarizing the benefits of using IVRs to deliver power to SoCs. Based on a simulation study targeting a 1.6W, 4-core SoC, I show that greater than 20% energy savings is possible with fast, per-core DVFS enabled by IVRs. Next, I present two stand-alone IVR test-chips converting 1.8V and 2.4V to 0.4-1.4V while delivering maximum 1W to the output. Both test-chips incorporate a 3-level VR topology, which is suitable for integration because the topology allows for much smaller inductors (1nH) than existing inductor-based buck VRs. I also discuss reasons behind lower-than-simulated efficiencies in the test-chips and ways to improve. Finally, I conclude with future process technologies that can boost IVR conversion efficiencies and power densities.Engineering and Applied Science

Doctor of Philosophy

dissertationMicroelectromechanical systems (MEMS) resonators on Si have the potential to replace the discrete passive components in a power converter. The main intention of this dissertation is to present a ring-shaped aluminum nitride (AlN) piezoelectric microreson

Designing an Optimum On-chip Inductor using Magnetic Core

학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 2. 김재하.벅컨버터 용 On-chip 인덕터의 성능 증가를 위한 마그네틱 코어 집적의 최적화를 제안한다. 마그네틱 코어는 closed-loop 이 아닌 open-loop 으로 형성돼 있으며, 평면상에서 코어의 면적이 최적화 변수에 들어간다. 최대한 closed-loop 에 가깝게 만들기 위해 평면상에서 칩에 구멍을 뚫어 수직 방향의 코어를 추가하였으며, 이러한 방식은 일반 CMOS 공정의 인덕터에도 마그네틱 코어를 집적할 수 있다는 장점이 있다. 그리고 HFSS 를 이용한 시뮬레이션을 통해 마그네틱 코어의 영향을 예측하고 이를 칩에 비해 구현하기 쉬운 PCB 인덕터로 검증한다. 그 후 칩으로 구현된 벅컨버터에 제안한 마그네틱 코어를 집적해 그 효과를 확인한다.목 차 초 록 1 목 차 2 제１장 서론 4 1.1 연구 목적 4 1.2 연구의 배경 4 1.3 논문의 구성 8 제２장 제안한 On-chip 인덕터의 마그네틱 코어 9 2.1 Square Spiral Inductor 9 2.2 제안한 마그네틱 코어 11 제３장 HFSS를 이용한 시뮬레이션 및 최적화 14 3.1 최적화 방법 및 인덕터 모델링 14 3.2 HFSS 시뮬레이션 결과 17 3.3 HFSS 결과를 이용한 인덕터 최적화 25 제４장 PCB 보드를 이용한 마그네틱 코어 효과 실험 38 4.1 Network Analyzer 를 사용한 L & R 측정 39 4.2 PCB 상의 벅컨버터 구성 및 마그네틱 코어에 따른 효율 변화 측정 40 제５장 CMOS 공정을 사용한 On-chip 인덕터 칩의 실험 결과 및 분석 42 5.1 칩에 마그네틱 코어 집적 방법 43 5.2 실험 결과 및 분석 45 제６장 결론 47 참고 문헌 48 Abstract 52Maste

Integrated circuits for efficient power delivery using pulse-width-modulation

Circuits and architectures for efficient power delivery have become crucial in emerging smart systems. Switching power amplifiers (PA) are very attractive for such applications, because they exhibit better efficiency compared to linear PA designs, due to saturated operation. Switching PAs also allow for utilization of deep submicron CMOS technologies, due to which these designs can be easily integrated with digital circuits, and can benefit from process scaling, in performance as well as in area. Pulse-width-modulation (PWM) is commonly used with switching PAs. A PWM signal typically employs a high-frequency switching pulse waveform as a carrier signal, wherein the pulse-width or duty-cycle of each pulse is modulated by a given low-frequency input signal. The carrier frequency can vary from several kHz to GHz, and is typically determined by the target application. In this thesis, efficient power-delivery circuits that use PWM with switching class-D stages are presented. Advanced circuit techniques, as well as architectures for PWM are proposed to enhance efficiency and circumvent the limitations of conventional architectures. A digitally-intensive transmitter using RF-PWM with a class-D PA is described in the first part of the thesis. The use of carrier switching for alleviating the dynamic range limitation that can be observed in classical RF-PWM implementations is introduced. The approach employs the full carrier frequency for half of the amplitude range, and the second harmonic of half of the carrier frequency, for the remainder of the amplitude range. This concept not only allows the transmitter to drive modulated signals with large peak-to-average power ratio (PAPR), but also improves the back-off efficiency due to reduced switching losses in the half carrier-frequency mode. A glitch-free phase selector is proposed that removes the deleterious glitches that can occur at the input data transitions. The phase-selector also prevents D flip-flop setup-and-hold time violations. The transmitter has been implemented in a 130-nm CMOS process. The measured peak output power and power-added-efficiency (PAE) are 25.6 dBm and 34%, respectively. While driving 802.11g 20-MHz 64-QAM OFDM signals, the average measured output power is 18.3 dBm and the PAE is 16%, with an EVM of -25.5 dB. The second part of the thesis describes a high-speed driver that provides a PWM output using a class-D PA. A PLL-based architecture is employed which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used for PWM generation. Multi-level signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high PAPR. A differential, folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with additional supply source and sink paths, compared to 2-level operation. The PWM driver has been implemented in a 130-nm CMOS process and can operate with a switching frequency of 40-to-170 MHz. For 2/3/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is -61/-62/-53 dB and corresponding efficiency is 71/83/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2/3-level PA operation with a high PAPR signal with 500 kHz bandwidth. While intended as a general purpose amplifier, the approach is well-suited for applications such as power-line communications (PLC). The final part of the thesis introduces an efficient buck/buck-boost reconfigurable LED driver that supports PWM and PFM operation. The driver is based on peak current control. Rectified sin as well as sin² functions are employed in the reference signal to improve the power factor (PF) and total harmonic distortion (THD) of the buck and buck-boost converters. The design ensures that the peak of the inductor current maintains a constant level that is invariant for different AC line voltages. The operating mode of the design can be changed between PWM and PFM. The LED driver has been implemented in a 130-nm CMOS process. PF and THD are improved when the proposed reference is employed, and peak PF and lowest THD are 0.995/0.983/0.996 and 7.8/6.2/3.5% for the buck (PWM), buck (PFM), buck-boost (PFM) cases, respectively. The corresponding peak efficiency for the three cases is 88/92/91%, respectively.Electrical and Computer Engineerin

Low Power Switched Capacitor DC-DC Converters for Low Power Transceiver Applications

DC-DC converters, also known as switching voltage regulators, are one of the main components of a power management unit. Their main role is to provide a constant, smooth output voltage to power the electronic devices. Recent miniaturi-zation trend of electronics circuitry has led to the need for smaller and high-efficient DC-DC converters in current and future applications. This thesis presents a Switched Capacitor (SC) based DC-DC converter, which can directly operate at input voltage of 4.2V on 45nm CMOS process. Currently, most of the DC-DC converters on 45nm are not able to operate at such high volt-ages. Moreover, SC architecture has resulted in smaller size of converter com-pared with LC type DC-DC converters. The design uses three SC topologies, which include two novel SC topologies of 2/5 and 2/7. Devices break down conditions have been overcome by implement-ing some of the MOS switches in cascoded structures. The converter structure uses eight phase interleaving approach to reduce output ripple to as low as 25mV level. In addition to the main SC structure, a four-stage differential ring oscillator is de-signed for providing quadrature clock signals to the SC topologies. Clock genera-tor can be enabled/disabled from outside the chip, through an enable (EN) pin. For instance, the EN pin can be used for regulating the output voltage in Pulse Fre-quency Modulation (PFM) feedback approach. /Kir1

Area- and Energy- Efficient Modular Circuit Architecture for 1,024-Channel Parallel Neural Recording Microsystem.

This research focuses to develop system architectures and associated electronic circuits for a next generation neuroscience research tool, a massive-parallel neural recording system capable of recording 1,024 channels simultaneously. Three interdependent prototypes have been developed to address major challenges in realization of the massive-parallel neural recording microsystems: minimization of energy and area consumption while preserving high quality in recordings. First, a modular 128-channel Δ-ΔΣ AFE using the spectrum shaping has been designed and fabricated to propose an area-and energy efficient solution for neural recording AFEs. The AFE achieved 4.84 fJ/C−s·mm2 figure of merit that is the smallest the area-energy product among the state-of-the-art multichannel neural recording systems. It also features power and area consumption of 3.05 µW and 0.05 mm2 per channel, respectively while exhibiting 63.3 dB signal-to-noise ratio with 3.02 µVrms input referred noise. Second, an on-chip mixed signal neural signal compressor was built to reduce the energy consumption in handling and transmission of the recorded data since this occupies a large portion of the total energy consumption as the number of parallel recording increases. The compressor reduces the data rates of two distinct groups of neural signals that are essential for neuroscience research: LFP and AP without loss of informative signals. As a result, the power consumptions for the data handling and transmissions of the LFP and AP were reduced to about 1/5.35 and 1/10.54 of the uncompressed cases, respectively. In the total data handling and transmission, the measured power consumption per channel is 11.98 µW that is about 1/9 of 107.5 µW without the compression. Third, a compact on-chip dc-to-dc converter with constant 1 MHz switching frequency has been developed to provide reliable power supplies and enhance energy delivery efficiency to the massive-parallel neural recording systems. The dc-to-dc converter has only predictable tones at the output and it exhibits > 80% power conversion efficiency at ultra-light loads, < 100 µW that is relevant power most of the multi-channel neural recording systems consume. The dc-to-dc converter occupies 0.375 mm2 of area which is less than 1/20 of the area the first prototype consumes (8.64 mm2).PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/133244/1/sungyun_1.pd