On the Bandstructure Velocity and Ballistic Current of Ultra Narrow Silicon Nanowire Transistors as a Function of Cross Section Size, Orientation and Bias

A 20 band sp3d5s* spin-orbit-coupled, semi-empirical, atomistic tight-binding (TB) model is used with a semi-classical, ballistic, field-effect-transistor (FET) model, to theoretically examine the bandstructure carrier velocity and ballistic current in silicon nanowire (NW) transistors. Infinitely long, uniform, cylindrical and rectangular NWs, of cross sectional diameters/sides ranging from 3nm to 12nm are considered. For a comprehensive analysis, n-type and p-type metal-oxide-semiconductor (NMOS and PMOS) NWs in [100], [110] and [111] transport orientations are examined. In general, physical cross section reduction increases velocities, either by lifting the heavy mass valleys, or significantly changing the curvature of the bands. The carrier velocities of PMOS [110] and [111] NWs are a strong function of diameter, with the narrower D=3nm wires having twice the velocities of the D=12nm NWs. The velocity in the rest of the NW categories shows only minor diameter dependence. This behavior is explained through features in the electronic structure of the silicon host material. The ballistic current, on the other hand, shows the least sensitivity with cross section in the cases where the velocity has large variations. Since the carrier velocity is a measure of the effective mass and reflects on the channel mobility, these results can provide insight into the design of NW devices with enhanced performance and performance tolerant to structure geometry variations. In the case of ballistic transport in high performance devices, the [110] NWs are the ones with both high NMOS and PMOS performance, as well as low on-current variations with cross section geometry variations.Comment: 31 pages, 7 figures, 1 tabl

Design space for low sensitivity to size variations in [110] PMOS nanowire devices: The implications of anisotropy in the quantization mass

A 20-band sp3d5s* spin-orbit-coupled, semi-empirical, atomistic tight-binding model is used with a semi-classical, ballistic, field-effect-transistor (FET) model, to examine the ON-current variations to size variations of [110] oriented PMOS nanowire devices. Infinitely long, uniform, rectangular nanowires of side dimensions from 3nm to 12nm are examined and significantly different behavior in width vs. height variations are identified and explained. Design regions are identified, which show minor ON-current variations to significant width variations that might occur due to lack of line width control. Regions which show large ON-current variations to small height variations are also identified. The considerations of the full band model here show that ON-current doubling can be observed in the ON-state at the onset of volume inversion to surface inversion transport caused by structural side size variations. Strain engineering can smooth out or tune such sensitivities to size variations. The cause of variations described is the structural quantization behavior of the nanowires, which provide an additional variation mechanism to any other ON-current variations such as surface roughness, phonon scattering etc.Comment: 24 pages, 5 figure

Electrical characterization and modeling of low dimensional nanostructure FET

At the beginning of this thesis, basic and advanced device fabrication process which I haveexperienced during study such as top-down and bottom-up approach for the nanoscale devicefabrication technique have been described. Especially, lithography technology has beenfocused because it is base of the modern device fabrication. For the advanced device structure,etching technique has been investigated in detail.The characterization of FET has been introduced. For the practical consideration in theadvanced FET, several parameter extraction techniques have been introduced such as Yfunction,split C-V etc.FinFET is one of promising alternatives against conventional planar devices. Problem ofFinFET is surface roughness. During the fabrication, the etching process induces surfaceroughness on the sidewall surfaces. Surface roughness of channel decreases the effectivemobility by surface roughness scattering. With the low temperature measurement andmobility analysis, drain current through sidewall and top surface was separated. From theseparated currents, effective mobilities were extracted in each temperature conditions. Astemperature lowering, mobility behaviors from the transport on each surface have differenttemperature dependence. Especially, in n-type FinFET, the sidewall mobility has strongerdegradation in high gate electric field compare to top surface. Quantification of surfaceroughness was also compared between sidewall and top surface. Low temperaturemeasurement is nondestructive characterization method. Therefore this study can be a propersurface roughness measurement technique for the performance optimization of FinFET.As another quasi-1 D nanowire structure device, 3D stacked SiGe nanowire has beenintroduced. Important of strain engineering has been known for the effective mobility booster.The limitation of dopant diffusion by strain has been shown. Without strain, SiGe nanowireFET showed huge short channel effect. Subthreshold current was bigger than strained SiGechannel. Temperature dependent mobility behavior in short channel unstrained device wascompletely different from the other cases. Impurity scattering was dominant in short channelunstrained SiGe nanowire FET. Thus, it could be concluded that the strain engineering is notnecessary only for the mobility booster but also short channel effect immunity.Junctionless FET is very recently developed device compare to the others. Like as JFET,junctionless FET has volume conduction. Thus, it is less affected by interface states.Junctionless FET also has good short channel effect immunity because off-state ofjunctionless FET is dominated pinch-off of channel depletion. For this, junctionless FETshould have thin body thickness. Therefore, multi gate nanowire structure is proper to makejunctionless FET.Because of the surface area to volume ratio, quasi-1D nanowire structure is good for thesensor application. Nanowire structure has been investigated as a sensor. Using numericalsimulation, generation-recombination noise property was considered in nanowire sensor.Even though the surface area to volume ration is enhanced in the nanowire channel, devicehas sensing limitation by noise. The generation-recombination noise depended on the channelgeometry. As a design tool of nanowire sensor, noise simulation should be carried out toescape from the noise limitation in advance.The basic principles of device simulation have been discussed. Finite difference method andMonte Carlo simulation technique have been introduced for the comprehension of devicesimulation. Practical device simulation data have been shown for examples such as FinFET,strongly disordered 1D channel, OLED and E-paper.At the beginning of this thesis, basic and advanced device fabrication process which I haveexperienced during study such as top-down and bottom-up approach for the nanoscale devicefabrication technique have been described. Especially, lithography technology has beenfocused because it is base of the modern device fabrication. For the advanced device structure,etching technique has been investigated in detail.The characterization of FET has been introduced. For the practical consideration in theadvanced FET, several parameter extraction techniques have been introduced such as Yfunction,split C-V etc.FinFET is one of promising alternatives against conventional planar devices. Problem ofFinFET is surface roughness. During the fabrication, the etching process induces surfaceroughness on the sidewall surfaces. Surface roughness of channel decreases the effectivemobility by surface roughness scattering. With the low temperature measurement andmobility analysis, drain current through sidewall and top surface was separated. From theseparated currents, effective mobilities were extracted in each temperature conditions. Astemperature lowering, mobility behaviors from the transport on each surface have differenttemperature dependence. Especially, in n-type FinFET, the sidewall mobility has strongerdegradation in high gate electric field compare to top surface. Quantification of surfaceroughness was also compared between sidewall and top surface. Low temperaturemeasurement is nondestructive characterization method. Therefore this study can be a propersurface roughness measurement technique for the performance optimization of FinFET.As another quasi-1 D nanowire structure device, 3D stacked SiGe nanowire has beenintroduced. Important of strain engineering has been known for the effective mobility booster.The limitation of dopant diffusion by strain has been shown. Without strain, SiGe nanowireFET showed huge short channel effect. Subthreshold current was bigger than strained SiGechannel. Temperature dependent mobility behavior in short channel unstrained device wascompletely different from the other cases. Impurity scattering was dominant in short channelunstrained SiGe nanowire FET. Thus, it could be concluded that the strain engineering is notnecessary only for the mobility booster but also short channel effect immunity.Junctionless FET is very recently developed device compare to the others. Like as JFET,junctionless FET has volume conduction. Thus, it is less affected by interface states.Junctionless FET also has good short channel effect immunity because off-state ofjunctionless FET is dominated pinch-off of channel depletion. For this, junctionless FETshould have thin body thickness. Therefore, multi gate nanowire structure is proper to makejunctionless FET.Because of the surface area to volume ratio, quasi-1D nanowire structure is good for thesensor application. Nanowire structure has been investigated as a sensor. Using numericalsimulation, generation-recombination noise property was considered in nanowire sensor.Even though the surface area to volume ration is enhanced in the nanowire channel, devicehas sensing limitation by noise. The generation-recombination noise depended on the channelgeometry. As a design tool of nanowire sensor, noise simulation should be carried out toescape from the noise limitation in advance.The basic principles of device simulation have been discussed. Finite difference method andMonte Carlo simulation technique have been introduced for the comprehension of devicesimulation. Practical device simulation data have been shown for examples such as FinFET,strongly disordered 1D channel, OLED and E-paper.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Quantum Transport in a Silicon Nanowire FET Transistor: Hot Electrons and Local Power Dissipation

A review and perspective is presented of the classical, semi-classical and fully quantum routes to the simulation of electro-thermal phenomena in ultra-scaled silicon nanowire field-effect transistors. It is shown that the physics of ultra-scaled devices requires at least a coupled electron quantum transport semi-classical heat equation model outlined here. The importance of the local density of states (LDOS) is discussed from classical to fully quantum versions. It is shown that the minimal quantum approach requires self-consistency with the Poisson equation and that the electronic LDOS must be determined within at least the self-consistent Born approximation. To bring in this description and to provide the energy resolved local carrier distributions it is necessary to adopt the non-equilibrium Green function (NEGF) formalism, briefly surveyed here. The NEGF approach describes quantum coherent and dissipative transport, Pauli exclusion and non-equilibrium conditions inside the device. There are two extremes of NEGF used in the community. The most fundamental is based on coupled equations for the Green functions electrons and phonons that are computed at the atomically resolved level within the nanowire channel and into the surrounding device structure using a tight binding Hamiltonian. It has the advantage of treating both the non-equilibrium heat flow within the electron and phonon systems even when the phonon energy distributions are not described by a temperature model. The disadvantage is the grand challenge level of computational complexity. The second approach, that we focus on here, is more useful for fast multiple simulations of devices important for TCAD (Technology Computer Aided Design). It retains the fundamental quantum transport model for the electrons but subsumes the description of the energy distribution of the local phonon sub-system statistics into a semi-classical Fourier heat equation that is sourced by the local heat dissipation from the electron system. It is shown that this self-consistent approach retains the salient features of the full-scale approach. For focus, we outline our electro-thermal simulations for a typical narrow Si nanowire gate all-around field-effect transistor. The self-consistent Born approximation is used to describe electron-phonon scattering as the source of heat dissipation to the lattice. We calculated the effect of the device self-heating on the current voltage characteristics. Our fast and simpler methodology closely reproduces the results of a more fundamental compute-intensive calculations in which the phonon system is treated on the same footing as the electron system. We computed the local power dissipation and “local lattice temperature” profiles. We compared the self-heating using hot electron heating and the Joule heating, i.e., assuming the electron system was in local equilibrium with the potential. Our simulations show that at low bias the source region of the device has a tendency to cool down for the case of the hot electron heating but not for the case of Joule heating. Our methodology opens the possibility of studying thermoelectricity at nano-scales in an accurate and computationally efficient way. At nano-scales, coherence and hot electrons play a major role. It was found that the overall behaviour of the electron system is dominated by the local density of states and the scattering rate. Electrons leaving the simulated drain region were found to be far from equilibrium

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Addressing performance bottlenecks for top-down engineered nanowire transistors

Ph.DDOCTOR OF PHILOSOPH

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

Caractérisation électrique des propriétés d'interface dans les MOSFET nanométriques par des mesures de bruit basse fréquence

In this thesis, electrical properties of gate oxide/channel interface in ultra-scaled nanowire (NW) MOSFETs were experimentally investigated by carrier transport and low-frequency noise (LFN) characterizations. NW FETs, which have aggressively downscaled cross-section of the body, are strong candidates for near future CMOS node. However, the interface quality could be a critical issue due to the large surface/volume ratio, the multiple surface orientations, and additional strain technology to enhance the performance. Understanding of carrier transport and channel interface quality in NW FETs with advanced high-k/metal gate is thus particularly important. LFN provides deep insights into the interface properties of MOSFET without lower limit of required channel size. LFN measurement thus can be a powerful technique for ultra-scaled NW FETs. Also, fitting mobility (such as low-field mobility) extraction by Y-function method is an efficient method. Omega-gate NW FETs were fabricated from FD-SOI substrates, and with Hf-based high-k/metal gate (HfSiON/TiN), reducing detrimental effects by device downscaling. In addition, strain technologies to the channel were additively processed. Tensile strained-SOI substrate was used for NMOS, whereas compressive stressors were used for PMOS devices. Strained Si channel for PMOS was processed by raised SiGe S/D and CESL formations. Strained SiGe channel (SGOI) was also fabricated for further high-performance PMOS FETs. Firstly, the most common Id-Vg was characterized in single-channel NW FETs as the basic performance. Reference SOI NWs provided the excellent static control down to short channel of 17nm. Stressors dramatically enhanced on-current owing to a modification of channel energy-band structure. Then, extracted low-field mobility in NWs also showed large improvement of the performance by stressors. The mobility extraction effectively evaluated FET performance even for ultra-scaled NWs. Next, LFN investigated for various technological and architectural parameters. Carrier number fluctuations with correlated mobility fluctuations (CNF+CMF) model described 1/f noise in all our FETs down to the shortest NWs. Drain current noise behavior was basically similar in both N- and PMOS FETs regardless of technological splits. Larger 1/f noise stemming from S/D regions in PMOS FETs was perfectly interpreted by the CNF+CMF model completed with Rsd fluctuations. This observation highlighted an advantage of SGOI NW with the lowest level of S/D region noise. Geometrical variations altered the CNF component with simple impact of device scaling (reciprocal to both Wtot and Lg). No large impact of surface orientation difference between the channel (100) top and (110) side-walls in [110]-oriented NWs was observed. Scaling regularity with both Wtot and Lg, without much quantum effect, could be attributed to the use of HfSiON/TiN gate and carrier transport occurring mostly near top and side-wall surfaces even in NW geometry. Meanwhile, the CMF factor was not altered by decreasing dimensions, while the mobility strongly depends on the impact. Extracted oxide trap density was roughly steady with scaling, structure, and technological parameter impacts. Simple separation method of the contributions between channel top surface and side-walls was demonstrated in order to evaluate the difference. It revealed that oxide quality on (100) top and (110) side-walls was roughly comparable in all the [110]-devices. The density values lie in similar order as the recent reports. An excellent quality of the interface with HfSiON/TiN gate was thus sustained for all our technological and geometrical splits. Finally, our NWs fulfilled 1/f LFN requirements stated in the ITRS 2013 for future MG CMOS logic node. Consequently, we concluded that appropriate strain technologies powerfully improve both carrier transport and LFN property for future CMOS circuits consisting of NW FETs, without any large concern about the interface quality.Dans cette thèse, les propriétés électriques de transistors à nanofils de silicium liées à l'interface oxyde de grille/canal ont été étudiées par le biais de mesures de bruit basse fréquence (bruit 1/f) et de transport dans le canal. Ces transistors nanofils dont les dimensions ont été réduites jusqu'à quelques nanomètres pour la section, représentent une alternative sérieuse pour les futurs nœuds technologiques CMOS. Cependant, la qualité de l'interface oxyde de grille/canal pose question pour transistors dont l'architecture s'étend dans les 3 dimensions, en raison du fort rapport surface/volume inhérent à ces transistors, des différentes orientations cristallographiques de ces interfaces, ou encore des matériaux contraints utilisés pour améliorer les performances électriques. La compréhension des liens entre les propriétés de transport des porteurs dans le canal, qui garantissent en grande partie les performances électriques des transistors, et la qualité de l'interface avec l'oxyde de grille est fond primordiale pour optimiser les transistors nanofils. Les mesures de bruit, associées à l'étude du transport dans le canal, sont un outil puissant et adapté à ces dispositifs tridimensionnels, sans être limité par la taille ultra-réduite des transistors nanofils. Les transistors nanofils étudiés ont été fabriqués à partir de substrats minces SOI, et intègrent un empilement de grille HfSiON/TiN, qui permet de réduire les dimensions tout en conservant les mêmes propriétés électrostatiques. Pour gagner en performances, des contraintes mécaniques ont été introduites dans le canal en silicium : en tension pour les NMOS, par le biais de substrat contraint (sSOI), et en compression pour les PMOS. Un canal en compression uni-axiale peut être obtenu par l'intégration de source/drain en SiGe et/ou par l'utilisation de couches contraintes de type CESL. Des transistors à canal SiGe sur isolant en compression ont également été fabriqués et étudiés. Les caractéristiques électriques des divers transistors nanofils (courbes Id-Vg, compromis Ion-Ioff, mobilité des porteurs) démontrent l'excellent contrôle électrostatique dû à l'architecture 3D, ainsi que l'efficacité de l'ingénierie de contraintes dans les nanofils jusqu'à de faibles longueurs de grilles (~17nm). Des mesures de bruit basse fréquence ont été réalisées sur ces mêmes dispositifs et analysées en fonction des paramètres géométriques de l'architecture nanofils (largeur W, forme de la section, longueur de grille L), et des diverses variantes technologiques. Nous avons démontré que le bruit 1/f dans les transistors nanofils peut être décrit par le modèle de fluctuations du nombre de porteurs (CNF) corrélées aux fluctuations de mobilité (CMF). Le bruit associé aux régions S/D a pu également être intégré dans ce modèle en ajoutant une contribution, en particulier pour les PMOS. Alors que les différentes variantes technologiques ont peu d'effet sur le bruit 1/f, les variations de géométrie en L et W changent la composante de bruit liée aux fluctuations du nombre de porteurs (CNF) de manière inversement proportionnelle à la surface totale (~1/WL). Cette augmentation du bruit est le reflet du transport qui se produit à proximité des interfaces avec l'oxyde. Les différentes orientations des interfaces supérieures et latérales (110) ou (100) présentent la même quantité de pièges d'interface (extrait à partir des mesures de bruit 1/f, en séparant les contributions des différentes faces du nanofil) bien qu'ayant une rugosité différente essentiellement liée au process. En revanche la composante CMF n'est pas altérée par la réduction des dimensions contrairement à la mobilité des porteurs qui décroit fortement avec L. Finalement, les mesures de bruit 1/f ont été comparées aux spécifications ITRS 2013 pour les transistors multi-grilles en vue des futurs nœuds technologiques de la logique CMOS, et démontrent que nos transistors nanofils satisfont les exigences en la matière

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

Quantum transport in a silicon nanowire FET transistor: hot electrons and local power dissipation

A review and perspective is presented of the classical, semiclassical and fully quantum routes to the simulation of electrothermal phenomena in ultrascaled silicon nanowire fieldeffect transistors. It is shown that the physics of ultrascaled devices requires at least a coupled electron quantum transport semiclassical heat equation model outlined here. The importance of the local density of states (LDOS) is discussed from classical to fully quantum versions. It is shown that the minimal quantum approach requires selfconsistency with the Poisson equation and that the electronic LDOS must be determined within at least the selfconsistent Born approximation. To bring in this description and to provide the energy resolved local carrier distributions it is necessary to adopt the nonequilibrium Green function (NEGF) formalism, briefly surveyed here. The NEGF approach describes quantum coherent and dissipative transport, Pauli exclusion and nonequilibrium conditions inside the device. There are two extremes of NEGF used in the community. The most fundamental is based on coupled equations for the Green functions electrons and phonons that are computed at the atomically resolved level within the nanowire channel and into the surrounding device structure using a tight binding Hamiltonian. It has the advantage of treating both the nonequilibrium heat flow within the electron and phonon systems even when the phonon energy distributions are not described by a temperature model. The disadvantage is the grand challenge level of computational complexity. The second approach, that we focus on here, is more useful for fast multiple simulations of devices important for TCAD (Technology Computer Aided Design). It retains the fundamental quantum transport model for the electrons but subsumes the description of the energy distribution of the local phonon subsystem statistics into a semiclassical Fourier heat equation that is sourced by the local heat dissipation from the electron system. It is shown that this selfconsistent approach retains the salient features of the fullscale approach. For focus, we outline our electrothermal simulations for a typical narrow Si nanowire gate allaround fieldeffect transistor. The selfconsistent Born approximation is used to describe electronphonon scattering as the source of heat dissipation to the lattice. We calculated the effect of the device selfheating on the current voltage characteristics. Our fast and simpler methodology closely reproduces the results of a more fundamental computeintensive calculations in which the phonon system is treated on the same footing as the electron system. We computed the local power dissipation and “local lattice temperature” profiles. We compared the selfheating using hot electron heating and the Joule heating, i.e., assuming the electron system was in local equilibrium with the potential. Our simulations show that at low bias the source region of the device has a tendency to cool down for the case of the hot electron heating but not for the case of Joule heating. Our methodology opens the possibility of studying thermoelectricity at nanoscales in an accurate and computationally efficient way. At nanoscales, coherence and hot electrons play a major role. It was found that the overall behaviour of the electron system is dominated by the local density of states and the scattering rate. Electrons leaving the simulated drain region were found to be far from equilibrium