Formalization of Fixed-Point Arithmetic in HOL

This paper addresses the formalization in higher-order logic of fixed-point arithmetic. We encoded the fixed-point number system and specified the different quantization modes in fixed-point arithmetic such as the directed and even quantization modes. We also considered the formalization of exceptions detection and their handling like overflow and invalid operation. An error analysis is then performed to check the correctness of the quantized result after carrying out basic arithmetic operations, such as addition, subtraction, multiplication and division against their mathematical counterparts. Finally, we showed by an example how this formalization can be used to enable the verification of the transition from floating-point to fixed-point algorithmic level in the signal processing design flow

Workshop on Verification and Theorem Proving for Continuous Systems (NetCA Workshop 2005)

Oxford, UK, 26 August 200

An approach for the formal verification of DSP designs using Theorem proving

This paper proposes a framework for the incorporation of formal methods in the design flow of digital signal processing (DSP) systems in a rigorous way. In the proposed approach, DSP descriptions were modeled and verified at different abstraction levels using higher order logic based on the higher order logic (HOL) theorem prover. This framework enables the formal verification of DSP designs that in the past could only be done partially using conventional simulation techniques. To this end, a shallow embedding of DSP descriptions in HOL at the floating-point (FP), fixed-point (FXP), behavioral, register transfer level (RTL), and netlist gate levels is provided. The paper made use of existing formalization of FP theory in HOL and a parallel one developed for FXP arithmetic. The high ability of abstraction in HOL allows a seamless hierarchical verification encompassing the whole DSP design path, starting from top-level FP and FXP algorithmic descriptions down to RTL, and gate level implementations. The paper illustrates the new verification framework on the fast Fourier transform (FFT) algorithm as a case study

Error analysis of digital filters using HOL theorem proving

When a digital filter is realized with floating-point or fixed-point arithmetics, errors and constraints due to finite word length are unavoidable. In this paper, we show how these errors can be mechanically analysed using the HOL theorem prover. We first model the ideal real filter specification and the corresponding floating-point and fixed-point implementations as predicates in higher-order logic. We use valuation functions to find the real values of the floating-point and fixed-point filter outputs and define the error as the difference between these values and the corresponding output of the ideal real specification. Fundamental analysis lemmas have been established to derive expressions for the accumulation of roundoff error in parametric Lth-order digital filters, for each of the three canonical forms of realization: direct, parallel, and cascade. The HOL formalization and proofs are found to be in a good agreement with existing theoretical paper-and-pencil counterparts

Formalization of Cadence SPW Fixed-Point Arithmetic in HOL

In this report we propose the formalization in higher-order logic of fixed-point arithmetic based on the SPW (Signal Processing WorkSystem) tool. We encoded the fixed-point number system and specified the different rounding modes in fixed-point arithmetic such as the directed and even rounding modes. We also considered the formalization of exceptions detection and their handling like overflow and invalid operation. An erro

Automated validation of minimum risk model-based system designs of complex avionics systems

Today, large civil aircraft incorporate a vast array of complex and coupled subsystems with thousands of electronic control units and software with millions of lines of code. Aircraft suppliers are challenged to provide superior products that are developed at a minimum time and cost, with maximum safety and security. No single person can understand the complex interactions of such a system of systems. Finding an optimal solution from large sets of different possible designs is an impossible task if done manually. Thus, written, non-executable specifications carry a high degree of product uncertainty. As a result, more than two-thirds of all specifications need to be reworked. Since most specification flaws are discovered and resolved at a late stage during development, when expenditures for redesign are at a maximum, the development approach currently used has a high probability of project cost and time overruns or even project failure, thus maximizing the risk of development. It is the aim of this work, to develop a model- and simulation-based systems engineering method with associated design and validation environment that minimizes the risk of development for complex systems, e.g. aircraft. The development risk is a minimum, if all development decisions are validated early against the services of a product at mission level by the final customer. To do so, executable specifications are created during design and validated against the requirements of system services at mission level. Validated executable specifications are used and updated for all decisions from concept development through implementation and training. In addition, virtual prototypes are developed. A virtual prototype is an executable system specification that is combined with human machine interface concept models to include usability requirements in the overall design and to enable interactive specification validation and early end user training by means of interactive user-driven system simulation. In a first step, so called executable workflows and simulation sets are developed to enable the execution of sets of structured and coupled simulation models. In a second step, a model- and simulation-based development and validation process model is developed from concept design to specification development. In a final step, two different validation processes are developed. An automated validation process based on executable specifications and an interactive validation process based on virtual prototypes. For the development of executable specifications and virtual prototypes, plug-and-play capable model components are developed. The developed method is validated for examples from civil aircraft development with focus on avionics and highly configurable and customizable cabin systems.Große zivile Flugzeuge umfassen eine hohe Anzahl von komplexen und gekoppelten Subsystemen mit Tausenden von elektronischen Steuergeräten und Software mit Millionen von Codezeilen. Keine einzelne Person kann die komplexen Wechselwirkungen eines solchen Systems von Systemen verstehen. Daher beinhalten geschriebene, nicht ausführbare Spezifikationen einen hohen Grad an Produktunsicherheit. Infolgedessen müssen mehr als zwei Drittel aller Spezifikationen überarbeitet werden. Da die meisten Spezifikationsfehler zu einem späten Zeitpunkt entdeckt und gelöst werden, wenn Aufwände für Überarbeitungen maximal sind, hat der gegenwärtige Entwicklungsansatz eine hohe Wahrscheinlichkeit für Kosten- und Zeitüberschreitungen oder führt zum Fehlschlagen von Projekten. Hierdurch wird das Entwicklungsrisiko maximiert. Es ist das Ziel dieser Arbeit, eine modell- und simulationsbasierte Entwicklungsmethode mit zugehöriger Entwurfs- und Validierungsumgebung zu entwickeln, welche das Risiko der Entwicklung für komplexe Systeme minimiert. Das Entwicklungsrisiko ist minimal, wenn alle Entwicklungsentscheidungen frühzeitig vom Endkunden gegen die Leistungen eines Produktes auf Missionsebene validiert werden. Dazu werden ausführbare Spezifikationen während des Entwurfs erstellt und anhand der Anforderungen auf Missionsebene validiert. Validierte ausführbare Spezifikationen werden für alle Entscheidungen von der Konzeptentwicklung bis zur Implementierung verwendet und aktualisiert. Darüber hinaus werden virtuelle Prototypen entwickelt, welche ausführbare Spezifikationen mit Konzeptmodellen für Mensch-Maschine-Schnittstellen kombinieren, um Usability-Anforderungen in den Gesamtentwurf aufzunehmen. Dies ermöglicht eine interaktive Validierung sowie frühes Endbenutzertraining mittels benutzergesteuerter Systemsimulation. Es werden ausführbare Arbeitsabläufe und Simulation Sets entwickelt, welche die Ausführung von strukturierten und gekoppelten Simulationsmodellen ermöglichen. Anschließend wird ein modell- und simulationsbasiertes Entwicklungs- und Validierungsprozessmodell vom Konzeptdesign bis zur Spezifikationsentwicklung entwickelt. Hierfür werden zwei verschiedene Validierungsprozesse verwendet. Ein automatisierter Validierungsprozess basierend auf ausführbaren Spezifikationen und ein interaktiver Validierungsprozess basierend auf virtuellen Prototypen. Für die Entwicklung von ausführbaren Spezifikationen und virtuellen Prototypen werden Modellkomponenten entwickelt. Die entwickelte Methode wird mithilfe von Beispielen aus der zivilen Flugzeugentwicklung validiert, insbesondere in Hinblick auf Avionik sowie hoch konfigurierbare und anpassbare Kabinensysteme