Electro-Mechanical Simulation of Switching Characteristics for Nanoelectromechanical Memory

The static switching properties and readout characteristics of proposed high-speed and nonvolatile nanoelectromechanical (NEM) memory devices are investigated By conducting a three-dimensional finite element mechanical simulation combined with an electrostatic analysis, we analyze the electromechanical switching operation of a mechanically bistable NEM floating gate by applying gate voltage. We show that switching voltage can be reduced to less than 10V by reducing the zero-bias displacement of the floating gate and optimizing the cavity structure to improve mechanical symmetry. We also analyze the electrical readout property of the NEM memory devices by combining the electromechanical simulation with a drift-diffusion analysis We demonstrate that the mechanically bistable states of the floating gate can be detected via the changes in drain current with an ON/OFF current ratio of about 3 x 10 (C) 2009 The Japan Society of Applied Physic

Numerical approach for retention characteristics of double floating-gate memories

We report on a numerical investigation in which memory characteristics of double floating-gate (DFG) structure were compared to those of the conventional single floating-gate structure, including an interference effect between two cells. We found that the advantage of the DFG structure is its longer retention time and the disadvantage is its smaller threshold voltage shift. We also provide an analytical form of charging energy including the interference effect.Comment: 4 pages, 4 figure

Increasing Flash Memory Lifetime by Dynamic Voltage Allocation for Constant Mutual Information

The read channel in Flash memory systems degrades over time because the Fowler-Nordheim tunneling used to apply charge to the floating gate eventually compromises the integrity of the cell because of tunnel oxide degradation. While degradation is commonly measured in the number of program/erase cycles experienced by a cell, the degradation is proportional to the number of electrons forced into the floating gate and later released by the erasing process. By managing the amount of charge written to the floating gate to maintain a constant read-channel mutual information, Flash lifetime can be extended. This paper proposes an overall system approach based on information theory to extend the lifetime of a flash memory device. Using the instantaneous storage capacity of a noisy flash memory channel, our approach allocates the read voltage of flash cell dynamically as it wears out gradually over time. A practical estimation of the instantaneous capacity is also proposed based on soft information via multiple reads of the memory cells.Comment: 5 pages. 5 figure

Electrical parameters extraction of CMOS floating-gate inverters

This work provides an accurate methodology for extracting the floating-gate gain factory, of CMOS floating-gate inverters with a clock-driven switch for accessing temporarilly to the floating-gate. With the methodology proposed in this paper, the γ factor and other parasitic capacitances coupled to the floating-gate can be easily extracted in a mismatch-free approach. This parameter plays an important role in modern analog and mixed-signal CMOS circuits, since it limits the circuit performance. Theoretical and measured values using two test cells, fabricated in a standard double poly double metal CMOS AMI-ABN process with 1.2 µm design rules, were compared. The extracted parameters can be incorporated into floating-gate PS pice macromodels for obtaining accurate electrical simulation

Current Mirror With Programmable Floating Gate

Systems and methods are discussed for using a floating-gate MOSFET as a programmable reference circuit. One example of the programmable reference circuit is a programmable voltage reference source, while a second example of a programmable reference circuit is a programmable reference current source. The programmable voltage reference source and/or the reference current source may be incorporated into several types of circuits, such as comparator circuits, current-mirror circuits, and converter circuits. Comparator circuits and current-mirror circuits are often incorporated into circuits such as converter circuits. Converter circuits include analog-to-digital converters and digital-to-analog converters.Georgia Tech Research Corporatio

FLASH MEMORY DEVICES WITH METAL FLOATING GATE/METAL NANOCRYSTALS AS THE CHARGE STORAGE LAYER: A STATUS REVIEW

Traditional flash memory devices consist of Polysilicon Control Gate (CG) – Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) – Polysilicon Floating Gate (FG) – Silicon Oxide (Tunnel dielectric) – Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge carrying information can be lost. The possible route to eliminate this problem is to use high-k based interpoly dielectric and to replace the polysilicon floating gate with a metal floating gate. At larger physical thickness, these materials have similar capacitance value hence avoiding tunneling effect.  Discrete nanocrystal memory has also been proposed to solve this problem. Due to its high operation speed, excellent scalability and higher reliability it has been shown as a promising candidate for future non-volatile memory applications. This review paper focuses on the recent efforts and research activities related to the fabrication and characterization of non-volatile memory device with metal floating gate/metal nanocrystals as the charge storage layer

Multilayer Layer Graphene Nanoribbon Flash Memory: Analysis of Programming and Erasing Operation

Flash memory based on floating gate transistor is the most widely used memory technology in modern microelectronic applications. We recently proposed a new concept of multilayer graphene nanoribbon (MLGNR) and carbon nanotube (CNT) based floating gate transistor design for future nanoscale flash memory technology. In this paper, we analyze the tunneling current mechanism in the proposed graphene-CNT floating gate transistor. We anticipate that the proposed floating gate transistor would adopt Fowler-Nordheim (FN) tunneling during its programming and erase operations. In this paper, we have investigated the mechanism of tunneling current and the factors that would influence this current and the behavior of the proposed floating gate transistor. The analysis reveals that FN tunneling is a strong function of the high field induced by the control gate, and the thicknesses of the control oxide and the tunnel oxide.Comment: in IEEE SOCC, Las Vegas, USA, 201

Arithmetic logic UNIT (ALU) design using reconfigurable CMOS logic

Using the reconfigurable logic of multi-input floating gate MOSFETs, a 4-bit ALU has been designed for 3V operation. The ALU can perform four arithmetic and four logical operations. Multi- input floating gate (MIFG) transistors have been promising in realizing increased functionality on a chip. A multi- input floating gate MOS transistor accepts multiple inputs signals, calculates the weighted sum of all input signals and then controls the ON and OFF states of the transistor. This enhances the transistor function to more than just switching. This changes the way a logic function can be realized. Implementing a design using multi-input floating gate MOSFETs brings about reduction in transis tor count and number of interconnections. The advantage of bringing down the number of devices is that a design becomes area efficient and power consumption reduces. There are several applications that stress on smaller chip area and reduced power. Multi- input floating gate devices have their use in memories, analog and digital circuits. In the present work we have shown successful implementation of multi- input floating gate MOSFETs in ALU design. A comparison has been made between adders using different design methods w.r.t transistor count. It is seen that our design, implemented using multi-input floating gate MOSFETs, uses the least number of transistors when compared to other designs. The design was fabricated using double polysilicon standard CMOS process by MOSIS in 1.5mm technology. The experimental waveforms and delay measurements have also been presented

Ternary logic to binary bit conversion using multiple input floating gate MOSFETS in 0.5 micron n-well CMOS technology

In the present work, a CMOS ternary to binary bit conversion technique has been proposed using multiple input floating gate MOSFETs. The proposed circuit has been implemented in 0.5 µm n-well CMOS technology. The ternary input signals of {-1, 0, +1} are represented as -3 V, 0 V and +3 V, respectively. The ternary input is given as a combination of any two of the three voltage levels and the 4-bit binary output is generated in which the left most bit is sign bit (SB) followed by most significant bit (MSB), second significant bit (SSB) and the least significant bit (LSB). The potential on the floating gate can be modified by either capacitive coupling with other conductors or by changing the stored charge on the floating gate. After each computation for a certain combination of inputs the floating gate carries a specific charge which has to be removed, or compensated for in order, to maintain integrity of the next computation. The four methods used commonly for modifying stored charge on the floating gate are UV radiation, tunneling, channel hot-electron injection and hopping through or trapping/de-trapping of charges. A simple method has been presented where the residual charge on the floating gate is by-passed and set to a certain biased initial value. Based on this initial value for the floating node voltage, the ratios of the values of the input capacitors which are capacitively coupled to the floating gate have been designed. The design was simulated in PSPICE and the output voltage at each stage of the converter was used to back calculate and model the ratios for the input capacitors as well as determine the biasing voltage on the floating gate