On the Investigation of a Novel Dual-Control-Gate Floating Gate Transistor for VCO Applications

A new MOS device called Dual-Control Gate Floating Gate Transistor (DCG-FGT) is used as a building block in analog design. This device offers new approaches in circuit design and allows developing new functionalities through two operating modes: Threshold Voltage Adjustable Mode, where the DCG-FGT behaves like a MOS transistor with an electrically adjustable threshold voltage. Mixer Signal Mode where the DCG-FGT can mix two independent signals on its floating gate. This device is developed to be fully compliant with CMOS Non Volatile Memory (NVM) process. An electrical model of the DCG-FGT has been implemented in an electrical simulator to be available for analog design. A DCG-FGT based ring oscillator is studied in this paper

On the Investigation of a Novel Dual-Control-Gate Floating Gate Transistor for VCO Applications

A new MOS device called Dual-Control Gate Floating Gate Transistor (DCG-FGT) is used as a building block in analog design. This device offers new approaches in circuit design and allows developing new functionalities through two operating modes: Threshold Voltage Adjustable Mode, where the DCG-FGT behaves like a MOS transistor with an electrically adjustable threshold voltage. Mixer Signal Mode where the DCG-FGT can mix two independent signals on its floating gate. This device is developed to be fully compliant with CMOS Non Volatile Memory (NVM) process. An electrical model of the DCG-FGT has been implemented in an electrical simulator to be available for analog design. A DCG-FGT based ring oscillator is studied in this paper

Charge-based compact model of gate-all-around floating gate nanowire with variable oxide thickness for flash memory cell

Due to high gate electrostatic control and introduction of punch and plug process technology, the gate-all-around (GAA) transistor is very promising in, and apparently has been utilized for, flash memory applications. However, GAA Floating Gate (GAA-FG) memory cell still requires high programming voltage that may be susceptible to cell-to-cell interference. Scaling down the tunnel oxide can reduce the Program/Erase (P/E) voltage but degrades the data retention capability. By using Technology-Computer-Aided-Design (TCAD) tools, the concept of tunnel barrier engineering using Variable Oxide Thickness (VARIOT) of low-k/high-k stack is utilized in compensating the trade-off between P/E operation and retention characteristics. Four high-k dielectrics (Si3N4, Al2O3, HfO2 and ZrO2) that are commonly used in semiconductor process technology are examined with SiO2 as its low-k dielectric. It is found that by using SiO2/Al2O3 as the tunnel layer, both the P/E and retention characteristics of GAA-FG can be compensated. About 30% improvement in memory window than conventional SiO2 is obtained and only 1% of charge-loss is predicted after 10 years of applying gate stress of -3.6V. Compact model of GAA-FG is initiated by developing a continuous explicit core model of GAA transistor (GAA Nanowire MOSFET (GAANWFET) and Juntionless Nanowire Transitor (JNT)). The validity of the theory and compact model is identified based on sophisticated numerical TCAD simulator for under 10% maximum error of surface potential. It is revealed that with the inclusion of partial-depletion conduction, the accuracy of the core model for GAANWFET is improved by more than 50% in the subthreshold region with doping-geometry ratio can be as high as about 0.86. As for JNT, despite the model being accurate for doping-geometry ratio upto 0.6, it is also independent of fitting parameters that may vary under different terminal biases or doping-geometry cases. The compact model of GAA-FG is completed by incorperating Charge Balance Model (CBM) into GAA transistor core model where good agreement is obtained with TCAD simulation and published experimental work. The CBM gives better accuracy than the conventional capacitive coupling approach under subthreshold region with approximately 10% error of floating gate potential. Therefore, the proposed compact model can be used to assist experimental work in extracting experimental data

A statistical study of time dependent reliability degradation of nanoscale MOSFET devices

Charge trapping at the channel interface is a fundamental issue that adversely affects the reliability of metal-oxide semiconductor field effect transistor (MOSFET) devices. This effect represents a new source of statistical variability as these devices enter the nano-scale era. Recently, charge trapping has been identified as the dominant phenomenon leading to both random telegraph noise (RTN) and bias temperature instabilities (BTI). Thus, understanding the interplay between reliability and statistical variability in scaled transistors is essential to the implementation of a ‘reliability-aware’ complementary metal oxide semiconductor (CMOS) circuit design. In order to investigate statistical reliability issues, a methodology based on a simulation flow has been developed in this thesis that allows a comprehensive and multi-scale study of charge-trapping phenomena and their impact on transistor and circuit performance. The proposed methodology is accomplished by using the Gold Standard Simulations (GSS) technology computer-aided design (TCAD)-based design tool chain co-optimization (DTCO) tool chain. The 70 nm bulk IMEC MOSFET and the 22 nm Intel fin-shape field effect transistor (FinFET) have been selected as targeted devices. The simulation flow starts by calibrating the device TCAD simulation decks against experimental measurements. This initial phase allows the identification of the physical structure and the doping distributions in the vertical and lateral directions based on the modulation in the inversion layer’s depth as well as the modulation of short channel effects. The calibration is further refined by taking into account statistical variability to match the statistical distributions of the transistors’ figures of merit obtained by measurements. The TCAD simulation investigation of RTN and BTI phenomena is then carried out in the presence of several sources of statistical variability. The study extends further to circuit simulation level by extracting compact models from the statistical TCAD simulation results. These compact models are collected in libraries, which are then utilised to investigate the impact of the BTI phenomenon, and its interaction with statistical variability, in a six transistor-static random access memory (6T-SRAM) cell. At the circuit level figures of merit, such as the static noise margin (SNM), and their statistical distributions are evaluated. The focus of this thesis is to highlight the importance of accounting for the interaction between statistical variability and statistical reliability in the simulation of advanced CMOS devices and circuits, in order to maintain predictivity and obtain a quantitative agreement with a measured data. The main findings of this thesis can be summarised by the following points: Based on the analysis of the results, the dispersions of VT and ΔVT indicate that a change in device technology must be considered, from the planar MOSFET platform to a new device architecture such as FinFET or SOI. This result is due to the interplay between a single trap charge and statistical variability, which has a significant impact on device operation and intrinsic parameters as transistor dimensions shrink further. The ageing process of transistors can be captured by using the trapped charge density at the interface and observing the VT shift. Moreover, using statistical analysis one can highlight the extreme transistors and their probable effect on the circuit or system operation. The influence of the passgate (PG) transistor in a 6T-SRAM cell gives a different trend of the mean static noise margin

Simulation of charge-trapping in nano-scale MOSFETs in the presence of random-dopants-induced variability

The growing variability of electrical characteristics is a major issue associated with continuous downscaling of contemporary bulk MOSFETs. In addition, the operating conditions brought about by these same scaling trends have pushed MOSFET degradation mechanisms such as Bias Temperature Instability (BTI) to the forefront as a critical reliability threat. This thesis investigates the impact of this ageing phenomena, in conjunction with device variability, on key MOSFET electrical parameters. A three-dimensional drift-diffusion approximation is adopted as the simulation approach in this work, with random dopant fluctuations—the dominant source of statistical variability—included in the simulations. The testbed device is a realistic 35 nm physical gate length n-channel conventional bulk MOSFET. 1000 microscopically different implementations of the transistor are simulated and subjected to charge-trapping at the oxide interface. The statistical simulations reveal relatively rare but very large threshold voltage shifts, with magnitudes over 3 times than that predicted by the conventional theoretical approach. The physical origin of this effect is investigated in terms of the electrostatic influences of the random dopants and trapped charges on the channel electron concentration. Simulations with progressively increased trapped charge densities—emulating the characteristic condition of BTI degradation—result in further variability of the threshold voltage distribution. Weak correlations of the order of 10-2 are found between the pre-degradation threshold voltage and post-degradation threshold voltage shift distributions. The importance of accounting for random dopant fluctuations in the simulations is emphasised in order to obtain qualitative agreement between simulation results and published experimental measurements. Finally, the information gained from these device-level physical simulations is integrated into statistical compact models, making the information available to circuit designers

Dynamics of biologically informed neural mass models of the brain

This book contributes to the development and analysis of computational models that help brain function to be understood. The mean activity of a brain area is mathematically modeled in such a way as to strike a balance between tractability and biological plausibility. Neural mass models (NMM) are used to describe switching between qualitatively different regimes (such as those due to pharmacological interventions, epilepsy, sleep, or context-induced state changes), and to explain resonance phenomena in a photic driving experiment. The description of varying states in an ordered sequence gives a principle scheme for the modeling of complex phenomena on multiple time scales. The NMM is matched to the photic driving experiment routinely applied in the diagnosis of such diseases as epilepsy, migraine, schizophrenia and depression. The model reproduces the clinically relevant entrainment effect and predictions are made for improving the experimental setting.Die vorliegende Arbeit stellt einen Beitrag zur Entwicklung und Analyse von Computermodellen zum Verständnis von Hirnfunktionen dar. Es wird die mittlere Aktivität eines Hirnareals analytisch einfach und dabei biologisch plausibel modelliert. Auf Grundlage eines Neuronalen Massenmodells (NMM) werden die Wechsel zwischen Oszillationsregimen (z.B. durch pharmakologisch, epilepsie-, schlaf- oder kontextbedingte Zustandsänderungen) als geordnete Folge beschrieben und Resonanzphänomene in einem Photic-Driving-Experiment erklärt. Dieses NMM kann sehr komplexe Dynamiken (z.B. Chaos) innerhalb biologisch plausibler Parameterbereiche hervorbringen. Um das Verhalten abzuschätzen, wird das NMM als Funktion konstanter Eingangsgrößen und charakteristischer Zeitenkonstanten vollständig auf Bifurkationen untersucht und klassifiziert. Dies ermöglicht die Beschreibung wechselnder Regime als geordnete Folge durch spezifische Eingangstrajektorien. Es wird ein Prinzip vorgestellt, um komplexe Phänomene durch Prozesse verschiedener Zeitskalen darzustellen. Da aufgrund rhythmischer Stimuli und der intrinsischen Rhythmen von Neuronenverbänden die Eingangsgrößen häufig periodisch sind, wird das Verhalten des NMM als Funktion der Intensität und Frequenz einer periodischen Stimulation mittels der zugehörigen Lyapunov-Spektren und der Zeitreihen charakterisiert. Auf der Basis der größten Lyapunov-Exponenten wird das NMM mit dem Photic-Driving-Experiment überein gebracht. Dieses Experiment findet routinemäßige Anwendung in der Diagnostik verschiedener Erkrankungen wie Epilepsie, Migräne, Schizophrenie und Depression. Durch die Anwendung des vorgestellten NMM wird der für die Diagnostik entscheidende Mitnahmeeffekt reproduziert und es werden Vorhersagen für eine Verbesserung der Indikation getroffen

The Mechanisms and Roles of Neural Feedback Loops for Visual Processing

Feedback pathways are widely present in various sensory systems transmitting time-delayed and partly-processed information from higher to lower visual centers. Although feedback loops are abundant in visual systems, investigations focusing on the mechanisms and roles of feedback in terms of micro-circuitry and system dynamics have been largely ignored. Here, we investigate the cellular, synaptic and circuit level properties of a cholinergic isthmic neuron: Ipc) to understand the role of isthmotectal feedback loop in visual processing of red-ear turtles, Trachemys scripta elegans. Turtle isthmotectal complex contains two distinct nuclei, Ipc and Imc, which interact exclusively with the optic tectum, but are otherwise isolated from other brain areas. The cholinergic Ipc neurons receive topographic glutamatergic inputs from tectal SGP neurons and project back to upper tectal layers in a topographic manner while GABAergic Imc neurons, which also get inputs from the SGP neurons project back non-topographically to both the tectum and Ipc nucleus. We have used an isolated eye-attached whole-brain preparation for our investigations of turtle isthmotectal feedback loop. We have investigated the cellular properties of the Ipc neurons by whole-cell blind-patch recordings and found that all Ipc neurons exhibit tonic firing responses to somatic current injections that are well-modeled by a leaky integrate-and-fire neuron with spike rate adaptation. Further investigations reveal that the optic nerve stimulations generate balanced excitatory and inhibitory synaptic currents in the Ipc neurons. We have also found that synaptic connection between the Imc to Ipc neuron is inhibitory. The visual response properties of the Ipc neurons to a range of computer-generated stimuli are investigated using extracellular recordings. We have found that the Ipc neurons have a localized excitatory receptive field and show stimulus selectivity and stimulus-size tuning. We also investigate lateral interactions in the Ipc neurons in response to multiple stimuli within the visual field. Finally, we quantify the oscillatory bursts observed in Ipc responses under visual stimulations

A Compositionality Machine Realized by a Hierarchic Architecture of Synfire Chains

The composition of complex behavior is thought to rely on the concurrent and sequential activation of simpler action components, or primitives. Systems of synfire chains have previously been proposed to account for either the simultaneous or the sequential aspects of compositionality; however, the compatibility of the two aspects has so far not been addressed. Moreover, the simultaneous activation of primitives has up until now only been investigated in the context of reactive computations, i.e., the perception of stimuli. In this study we demonstrate how a hierarchical organization of synfire chains is capable of generating both aspects of compositionality for proactive computations such as the generation of complex and ongoing action. To this end, we develop a network model consisting of two layers of synfire chains. Using simple drawing strokes as a visualization of abstract primitives, we map the feed-forward activity of the upper level synfire chains to motion in two-dimensional space. Our model is capable of producing drawing strokes that are combinations of primitive strokes by binding together the corresponding chains. Moreover, when the lower layer of the network is constructed in a closed-loop fashion, drawing strokes are generated sequentially. The generated pattern can be random or deterministic, depending on the connection pattern between the lower level chains. We propose quantitative measures for simultaneity and sequentiality, revealing a wide parameter range in which both aspects are fulfilled. Finally, we investigate the spiking activity of our model to propose candidate signatures of synfire chain computation in measurements of neural activity during action execution