Structure and realization of pole-shared switched-current complex wavelet filter

A pole-shared switched-current complex wavelet filter structure with follow-the-leader feedback configuration is proposed for synthesizing the real and imaginary approximation functions with the same poles. The double-sampling fully-balanced SI bilinear integrator and current mirror are employed as the building cells. By sharing the implementation circuit for approximation poles of the real and the imaginary part, the proposed structure only has the same circuit complexity as that of real-valued wavelet filter, which is very suitable for small-size and low-power application. The complex Morlet wavelet is selected as an example to elaborate the design procedure. Simulation results confirm that the presented complex wavelet filter structure can generate the real and imaginary coefficients of complex wavelet transform accurately with simple synthesis method and explicit design formulas.Peer reviewedFinal Accepted Versio

Multiplierless perfect reconstruction modulated filter banks with sum-of-powers-of-two coefficients

This paper proposes an efficient class of perfect reconstruction (PR) modulated filter banks (MFB) using sum-of-powers-of-two (SOPOT) coefficients. This is based on a modified factorization of the DCT-IV matrix and the lossless latrice structure of the prototype filter, which allows the coefficients to be represented in SOPOT form without affecting the PR condition. A genetic algorithm (GA) is then used to search for these SOPOT coefficients. Design examples show that SOPOT MFB with a good frequency characteristic can be designed with very low implementation complexity. The usefulness of the approach is demonstrated with a 16-channel design example.published_or_final_versio

A new class of two-channel biorthogonal filter banks and wavelet bases

We propose a novel framework for a new class of two-channel biorthogonal filter banks. The framework covers two useful subclasses: i) causal stable IIR filter banks. ii) linear phase FIR filter banks. There exists a very efficient structurally perfect reconstruction implementation for such a class. Filter banks of high frequency selectivity can be achieved by using the proposed framework with low complexity. The properties of such a class are discussed in detail. The design of the analysis/synthesis systems reduces to the design of a single transfer function. Very simple design methods are given both for FIR and IIR cases. Zeros of arbitrary multiplicity at aliasing frequency can be easily imposed, for the purpose of generating wavelets with regularity property. In the IIR case, two new classes of IIR maximally flat filters different from Butterworth filters are introduced. The filter coefficients are given in closed form. The wavelet bases corresponding to the biorthogonal systems are generated. the authors also provide a novel mapping of the proposed 1-D framework into 2-D. The mapping preserves the following: i) perfect reconstruction; ii) stability in the IIR case; iii) linear phase in the FIR case; iv) zeros at aliasing frequency; v) frequency characteristic of the filters

FIR variable digital filter with signed power-of-two coefficients

Variable digital filters (VDFs) are useful for various signal processing and communication applications where the frequency characteristics, such as fractional delays and cutoff frequencies, can be varied online. In this paper, we investigate the design of VDFs with discrete coefficients as a means of achieving low complexity and efficient hardware implementation. The filter coefficients are expressed as the sum of signed power-of-two terms with a restriction on the total number of power-of-two for the filter coefficients. An efficient design procedure is proposed that includes an improved method for handling the quantization of the VDF coefficients for both the min-max and the least-square criteria leading to an optimum quantized solution. For the least-square criterion, a reduced search region around the optimum quantized solution is further constructed and the branch and bound method in conjunction with an efficient branch cutting scheme is presented to search for an optimum solution in this reduced region

Low Complexity Multiplier-less Modified FRM Filter Bank using MPGBP Algorithm

The design of a low complexity multiplier-less narrow transition band filter bank for the channelizer of multi-standard software-defined radio (SDR) is investigated in this paper. To accomplish this, the modal filter and complementary filter in the upper and lower branches of the conventional Frequency Response Masking (FRM) architecture are replaced with two power-complementary and linear phase filter banks. Secondly, a new masking strategy is proposed to fully exploit the potential of the numerous spectra replicas produced by the interpolation of the modal filter, which was previously ignored in the existing FRM design. In this scheme, the two masking filters are appropriately modulated and alternately masked over the spectra replicas from 0 to 2$\pi$, to generate even and odd channels. This Alternate Masking Scheme (AMS) increases the potency of the Modified FRM (ModFRM) architecture for the design of a computationally efficient narrow transition band uniform filter bank (termed as ModFRM-FB). Finally, by combining the adjoining ModFRM-FB channels, Non-Uniform ModFRM-FB (NUModFRM-FB) for extracting different communication standards in the SDR channelizer is created. To reduce the total power consumption of the architecture, the coefficients of the proposed system are made multiplier-less using the Matching Pursuits Generalized Bit-Planes (MPGBP) algorithm. In this method, filter coefficients are successively approximated using a dictionary of vectors to give a sum-of-power-of-two (SOPOT) representation. In comparison to all other general optimization techniques, such as genetic algorithms, the suggested design method stands out for its ease of implementation, requiring no sophisticated optimization or exhaustive search schemes. Another notable feature of the suggested approach is that, in comparison to existing methods, the design time for approximation has been greatly reduced. To further bring down the complexity, adders are reused in recurrent SOPOT terms using the Common Sub-expression Elimination (CSE) technique without compromising the filter performance

Design and multiplier-less realization of matched filters with variable fractional delay for software radio receivers

The 47th Midwest Symposium on Circuits and Systems Conference, Salt Lake City, Utah, USA, 25-28 July 2004This paper studies the design and multiplier-less realization of variable fractional delay matched filters (VFD-MFs), which provide matching filtering and variable fractional delay of the filter output. It offers greater flexibility and lower delay in symbol-timing adjustment than directly cascading a match filter with a fractional delayer. The design of VFD-MFs, which can be viewed as a variable digital filter (VDF) design problem subject to the matched filtering condition, is formulated as a second order cone programming (SOCP) problem with least square design criteria. The proposed VFD-MFs can be efficiently implemented using the Farrow structure. By employing sum-of-power-of-two (SOPOT) coefficients and the multiplier block (MB) technique, very efficient multiplier-less realization of the VFD-MF with low hardware complexity is obtained. A design example is given to demonstrate the effectiveness of the proposed approach.published_or_final_versio

Low Complexity Multiplier-less Modified FRM Filter Bank using MPGBP Algorithm

The design of a low complexity multiplier-less narrow transition band filter bank for the channelizer of multi-standard software-defined radio (SDR) is investigated in this paper. To accomplish this, the modal filter and complementary filter in the upper and lower branches of the conventional Frequency Response Masking (FRM) architecture are replaced with two power-complementary and linear phase filter banks. Secondly, a new masking strategy is proposed to fully exploit the potential of the numerous spectra replicas produced by the interpolation of the modal filter, which was previously ignored in the existing FRM design. In this scheme, the two masking filters are appropriately modulated and alternately masked over the spectra replicas from 0 to 2$\pi$, to generate even and odd channels. This Alternate Masking Scheme (AMS) increases the potency of the Modified FRM (ModFRM) architecture for the design of a computationally efficient narrow transition band uniform filter bank (termed as ModFRM-FB). Finally, by combining the adjoining ModFRM-FB channels, Non-Uniform ModFRM-FB (NUModFRM-FB) for extracting different communication standards in the SDR channelizer is created. To reduce the total power consumption of the architecture, the coefficients of the proposed system are made multiplier-less using the Matching Pursuits Generalized Bit-Planes (MPGBP) algorithm. In this method, filter coefficients are successively approximated using a dictionary of vectors to give a sum-of-power-of-two (SOPOT) representation. In comparison to all other general optimization techniques, such as genetic algorithms, the suggested design method stands out for its ease of implementation, requiring no sophisticated optimization or exhaustive search schemes. Another notable feature of the suggested approach is that, in comparison to existing methods, the design time for approximation has been greatly reduced. To further bring down the complexity, adders are reused in recurrent SOPOT terms using the Common Sub-expression Elimination (CSE) technique without compromising the filter performance

Single-bit adaptive channel equalization for narrowband signals

In this paper, a new design of a single-bit adaptive channel equalization is proposed using sigma delta modulation and a single-bit block Least Mean Square (LMS) algorithm. With correlated narrowband input signals, this model is capable to converge and provide equivalent equalization filter with improvement in the SNR and very low Symbol Error Rate (SER). The input, filter coefficients and output values are all in single-bit and ternary format that results in a reduction in hardware complexity compared to traditional multi-bit channel equalization. Additionally, the technique avoids the need for successive conversion from multi-bit to single bit and back at the receiver and transmitter stages

Fir filter design for area efficient implementation /

In this dissertation, a variable precision algorithm based on sensitivity analysis is proposed for reducing the wordlength of the coefficients and/or the number of nonzero bits of the coefficients to reduce the complexity required in the implementation. Further space savings is possible if the proposed algorithm is associated with our optimal structures and derived scaling algorithm. We also propose a structure to synthesize FIR filters using the improved prefilter equalizer structure with arbitrary bandwidth, and our proposed filter structure reduces the area required. Our improved design is targeted at improving the prefilters based on interpolated FIR filter and frequency masking design and aims to provide a sharp transition-band as well as increasing the stopband attenuation. We use an equalizer designed to compensate the prefilter performance. In this dissertation, we propose a systematic procedure for designing FIR filters implementations. Our method yields a good design with low coefficient sensitivity and small order while satisfying design specifications. The resulting hardware implementation is suitable for use in custom hardware such as VLSI and Field Programmable Gate Arrays (FPGAs).FIR filters are preferred for many Digital Signal Processing applications as they have several advantages over IIR filters such as the possibility of exact linear phase, shorter required wordlength and guaranteed stability. However, FIR filter applications impose several challenges on the implementations of the systems, especially in demanding considerably more arithmetic operations and hardware components. This dissertation focuses on the design and implementation of FIR filters in hardware to reduce the space required without loss of performance

Design and multiplier-less implementation of a class of two-channel PR FIR filterbanks and wavelets with low system delay

In this paper, a new method for designing two-channel PR FIR filterbanks with low system delay is proposed. It is based on the generalization of the structure previously proposed by Phoong et al. Such structurally PR filterbanks are parameterized by two functions (β(z) and α(z)) that can be chosen as linear-phase FIR or allpass functions to construct FIR/IIR filterbanks with good frequency characteristics. The case of using identical β(z) and α(z) was considered by Phoong et al. with the delay parameter M chosen as 2N - 1. In this paper, the more general case of using different nonlinear-phase FIR functions for β(z) and α(z) is studied. As the linear-phase constraint is relaxed, the lengths of β(z) and α(z) are no longer restricted by the delay parameters of the filterbanks. Hence, higher stopband attenuation can still be achieved at low system delay. The design of the proposed low-delay filterbanks is formulated as a complex polynomial approximation problem, which can be solved by the Remez exchange algorithm or analytic formula with very low complexity. In addition, the orders and delay parameters can be estimated from the given filter specifications using a simple empirical formula. Therefore, low-delay two-channel PR filterbanks with flexible stopband attenuation and cutoff frequencies can be designed using existing filter design algorithms. The generalization of the present approach to the design of a class of wavelet bases associated with these low-delay filterbanks and its multiplier-less implementation using the sum of powers-of-two coefficients are also studied.published_or_final_versio