Application of a Genetic Algorithm in a Fault-tolerant Filter

This paper presents an eighth order low-pass filter which has characteristics of fault tolerance through the use of evolvable hardware (EHW). A field programmable analog array (FPAA) is used to implement the filter under study. The reconfiguration process of the filter involves the execution of a genetic algorithm (GA) in an external computer, after a fault is detected. To perform the test of the filter, we assume that a frequency response characterization test is used. A parametric fault model that considers deviations in the values of one of the capacitors or one of the input amplifiers (IA) is used to evaluate the performance of developed GA. The results show that GA finds filter configurations that meet the restrictions set for all the simulated faults. Additionally, this work shows better results compared to those previously obtained using another EHW scheme for the same low-pass filter.Sociedad Argentina de Informática e Investigación Operativ

Application of a Genetic Algorithm in a Fault-tolerant Filter

This paper presents an eighth order low-pass filter which has characteristics of fault tolerance through the use of evolvable hardware (EHW). A field programmable analog array (FPAA) is used to implement the filter under study. The reconfiguration process of the filter involves the execution of a genetic algorithm (GA) in an external computer, after a fault is detected. To perform the test of the filter, we assume that a frequency response characterization test is used. A parametric fault model that considers deviations in the values of one of the capacitors or one of the input amplifiers (IA) is used to evaluate the performance of developed GA. The results show that GA finds filter configurations that meet the restrictions set for all the simulated faults. Additionally, this work shows better results compared to those previously obtained using another EHW scheme for the same low-pass filter.Sociedad Argentina de Informática e Investigación Operativ

Evolutionary morphogenesis for multi-cellular systems

With a gene required for each phenotypic trait, direct genetic encodings may show poor scalability to increasing phenotype length. Developmental systems may alleviate this problem by providing more efficient indirect genotype to phenotype mappings. A novel classification of multi-cellular developmental systems in evolvable hardware is introduced. It shows a category of developmental systems that up to now has rarely been explored. We argue that this category is where most of the benefits of developmental systems lie (e.g. speed, scalability, robustness, inter-cellular and environmental interactions that allow fault-tolerance or adaptivity). This article describes a very simple genetic encoding and developmental system designed for multi-cellular circuits that belongs to this category. We refer to it as the morphogenetic system. The morphogenetic system is inspired by gene expression and cellular differentiation. It focuses on low computational requirements which allows fast execution and a compact hardware implementation. The morphogenetic system shows better scalability compared to a direct genetic encoding in the evolution of structures of differentiated cells, and its dynamics provides fault-tolerance up to high fault rates. It outperforms a direct genetic encoding when evolving spiking neural networks for pattern recognition and robot navigation. The results obtained with the morphogenetic system indicate that this "minimalist” approach to developmental systems merits further stud

Improving Artificial-Immune-System-based computing by exploiting intrinsic features of computer architectures

Biological systems have become highly significant for traditional computer architectures as examples of highly complex self-organizing systems that perform tasks in parallel with no centralized control. However, few researchers have compared the suitability of different computing approaches for the unique features of Artificial Immune Systems (AIS) when trying to introduce novel computing architectures, and few consider the practicality of their solutions for real world machine learning problems. We propose that the efficacy of AIS-based computing for tackling real world datasets can be improved by the exploitation of intrinsic features of computer architectures. This paper reviews and evaluates current existing implementation solutions for AIS on different computing paradigms and introduces the idea of “C Principles” and “A Principles”. Three Artificial Immune Systems implemented on different architectures are compared using these principles to examine the possibility of improving AIS through taking advantage of intrinsic hardware features

SABRE: A bio-inspired fault-tolerant electronic architecture

As electronic devices become increasingly complex, ensuring their reliable, fault-free operation is becoming correspondingly more challenging. It can be observed that, in spite of their complexity, biological systems are highly reliable and fault tolerant. Hence, we are motivated to take inspiration for biological systems in the design of electronic ones. In SABRE (self-healing cellular architectures for biologically inspired highly reliable electronic systems), we have designed a bio-inspired fault-tolerant hierarchical architecture for this purpose. As in biology, the foundation for the whole system is cellular in nature, with each cell able to detect faults in its operation and trigger intra-cellular or extra-cellular repair as required. At the next level in the hierarchy, arrays of cells are configured and controlled as function units in a transport triggered architecture (TTA), which is able to perform partial-dynamic reconfiguration to rectify problems that cannot be solved at the cellular level. Each TTA is, in turn, part of a larger multi-processor system which employs coarser grain reconfiguration to tolerate faults that cause a processor to fail. In this paper, we describe the details of operation of each layer of the SABRE hierarchy, and how these layers interact to provide a high systemic level of fault tolerance. © 2013 IOP Publishing Ltd

Intrinsically Evolvable Artificial Neural Networks

Dedicated hardware implementations of neural networks promise to provide faster, lower power operation when compared to software implementations executing on processors. Unfortunately, most custom hardware implementations do not support intrinsic training of these networks on-chip. The training is typically done using offline software simulations and the obtained network is synthesized and targeted to the hardware offline. The FPGA design presented here facilitates on-chip intrinsic training of artificial neural networks. Block-based neural networks (BbNN), the type of artificial neural networks implemented here, are grid-based networks neuron blocks. These networks are trained using genetic algorithms to simultaneously optimize the network structure and the internal synaptic parameters. The design supports online structure and parameter updates, and is an intrinsically evolvable BbNN platform supporting functional-level hardware evolution. Functional-level evolvable hardware (EHW) uses evolutionary algorithms to evolve interconnections and internal parameters of functional modules in reconfigurable computing systems such as FPGAs. Functional modules can be any hardware modules such as multipliers, adders, and trigonometric functions. In the implementation presented, the functional module is a neuron block. The designed platform is suitable for applications in dynamic environments, and can be adapted and retrained online. The online training capability has been demonstrated using a case study. A performance characterization model for RC implementations of BbNNs has also been presented