Testability Analysis of Synchronous Sequential Circuits Based On Structural Data

Bounds on test sequence length can be used as a testability measure. We give a procedure to compute the upper bound on test sequence length for an arbitrary sequential circuit. We prove that the bound is exact for a certain class of circuits. Three design rules are specified to yield circuits with lower test sequence bounds

On the construction of hierarchic models

One of the main problems in the field of model-based diagnosis of technical systems today is finding the most useful model or models of the system being diagnosed. Often, a model showing the physical components and the connections between them is all that is available. As systems grow larger and larger, the run-time performance of diagnostic algorithms decreases considerably when using these detailed models. A solution to this problem is using a hierarchic model. This allows us to first diagnose the system using an abstract model, and then use this solution to guide the diagnostic process using a more detailed model. The main problem with this approach is acquiring the hierarchic model. We give a generic hierarchic diagnostic algorithm and show how the use of certain classes of hierarchic models can increase the performance of this algorithm. We then present linear time algorithms for the automatic construction of these hierarchic models, using the detailed model and extra information about cost of probing points and invertibility of components

Efficient VLSI fault simulation

AbstractLet C be an acyclic Boolean circuit with n gates and ≤ n inputs. A circuit manufacture error may result in a “Stuck-at” (S-A) fault in a circuit identical to C except a gate v only outputs a fixed Boolean value. The S-A fault simulation problem for C is to determine all possible (S-A) faults which can be detected (i.e., faults circuit and C would give distinct outputs) by a given test pattern input.We consider the case where C is a tree (i.e., has fan-out 1.)We give a practical algorithm for fault simulation which simultaneously determines all detectable S-A faults for every gate in the circuit tree C. Our algorithm required only the evaluation of a circuit FS(C) which has ≤ 7n gates and has depth ≤ 3(d + 1), when d is the depth of C. Thus the sequential time of our algorithm is ≤ 7n, and the parallel time is ≤ 3(d + 1). Furthermore, FS(C) requires only a small constant factor more VLSI area than does the original circuit C.We also extend our results to get efficient methods for fault simulation of oblivious VLSI circuits with feedback lines

A Hardware Security Solution against Scan-Based Attacks

Scan based Design for Test (DfT) schemes have been widely used to achieve high fault coverage for integrated circuits. The scan technique provides full access to the internal nodes of the device-under-test to control them or observe their response to input test vectors. While such comprehensive access is highly desirable for testing, it is not acceptable for secure chips as it is subject to exploitation by various attacks. In this work, new methods are presented to protect the security of critical information against scan-based attacks. In the proposed methods, access to the circuit containing secret information via the scan chain has been severely limited in order to reduce the risk of a security breach. To ensure the testability of the circuit, a built-in self-test which utilizes an LFSR as the test pattern generator (TPG) is proposed. The proposed schemes can be used as a countermeasure against side channel attacks with a low area overhead as compared to the existing solutions in literature

Test set generation almost for free using a Run-Time FPGA reconfiguration technique

The most important step in the final testing of fabricated ASICs or the functional testing of ASIC and FPGA designs is the generation of a complete test set that is able to find the possible errors in the design. Automatic Test Pattern Generation (ATPG) is often done by fault simulation which is very time-consuming. Speed-ups in this process can be achieved by emulating the design on an FPGA and using the actual speed of the hardware implementation to run proposed tests. However, faults then have to be actually built in into the design, which induces area overhead as (part of) the design has to be duplicated to introduce both a faulty and a correct design. The area overhead can be mitigated by run-time reconfiguring the design, at the expense of large reconfiguration time overheads. In this paper, we leverage the parameterised reconfiguration of FPGAs to create an efficient Automatic Test Pattern Generator with very low overhead in both area and time. Experimental results demonstrate the practicality of the new technique as, compared to conventional tools, we obtain speedups of up to 3 orders of magnitude, 8X area reduction, and no increase in critical path delay